JPS57199058A - Controlling system for microprogram - Google Patents

Controlling system for microprogram

Info

Publication number
JPS57199058A
JPS57199058A JP56084820A JP8482081A JPS57199058A JP S57199058 A JPS57199058 A JP S57199058A JP 56084820 A JP56084820 A JP 56084820A JP 8482081 A JP8482081 A JP 8482081A JP S57199058 A JPS57199058 A JP S57199058A
Authority
JP
Japan
Prior art keywords
failure
information
rams
stored
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56084820A
Other languages
Japanese (ja)
Inventor
Yasuo Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56084820A priority Critical patent/JPS57199058A/en
Publication of JPS57199058A publication Critical patent/JPS57199058A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To detect an exact internal state at failure generation, by selecting an arbitrary one out of a plurality of storage means in accordance with the situation where various control informations are stored to a plurality of storage means simultaneously and a failure is detected. CONSTITUTION:In writing information to an RAM2 with a normal mu program operation, the content of a data register 7 is stored in a designated address with an address register 6, FFs 12-14 are set to 0, and the same information is written in RAMs 3-5 at the same time. If a failure detecting circuit 8 detects a failure, the FFs 12-14 are set according to the types of failures, the writing to the RAMs 3-5 is inhibited and the same content as the RAM2 at the production of a failure is stored in the RAMs 3-5. When required failure information is desired to be read out, and when a prescribed value is set to an RAM output selecting register 20, one of the outputs of the RAMs 3-5 is selected at a selection circuit 18 and an FF21 is set, the information is stored in the register 7 with a selection circuit 19, allowing to obtain useful failure analysis information.
JP56084820A 1981-06-01 1981-06-01 Controlling system for microprogram Pending JPS57199058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56084820A JPS57199058A (en) 1981-06-01 1981-06-01 Controlling system for microprogram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56084820A JPS57199058A (en) 1981-06-01 1981-06-01 Controlling system for microprogram

Publications (1)

Publication Number Publication Date
JPS57199058A true JPS57199058A (en) 1982-12-06

Family

ID=13841379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56084820A Pending JPS57199058A (en) 1981-06-01 1981-06-01 Controlling system for microprogram

Country Status (1)

Country Link
JP (1) JPS57199058A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS638804A (en) * 1986-06-27 1988-01-14 Koyo Denshi Kogyo Kk Programmable controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148449A (en) * 1978-05-15 1979-11-20 Fujitsu Ltd Tracer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148449A (en) * 1978-05-15 1979-11-20 Fujitsu Ltd Tracer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS638804A (en) * 1986-06-27 1988-01-14 Koyo Denshi Kogyo Kk Programmable controller

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