JPS5687147A - Data recorder - Google Patents

Data recorder

Info

Publication number
JPS5687147A
JPS5687147A JP16444179A JP16444179A JPS5687147A JP S5687147 A JPS5687147 A JP S5687147A JP 16444179 A JP16444179 A JP 16444179A JP 16444179 A JP16444179 A JP 16444179A JP S5687147 A JPS5687147 A JP S5687147A
Authority
JP
Japan
Prior art keywords
address
signal
data
bus
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16444179A
Other languages
Japanese (ja)
Inventor
Nobuo Terachi
Takeo Ikeda
Fumiaki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16444179A priority Critical patent/JPS5687147A/en
Publication of JPS5687147A publication Critical patent/JPS5687147A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To perform failure processing in a short time, by reading out a signal recorded at the production of failure and reproducing the state of failure production point at a specific area, through the recording of data continuously only in the address area designating the signal on the bus.
CONSTITUTION: In recording the data transferred to the recorder 1, the address on the address bus 2-1 is stored to the address memory 6, and the data on the data bus 2-2 is stored to the data memory 7. Further, the address of information to be recorded to the address set section 10 is set. Further, the address on the bus 2 and the control signal are input to the controller 8, and only the preset address is processed for the write-in signal to the memories 6, 7 from the controller 8 every address, and the count-up signal is fed to the counter 9, the memory address of the memories 6, 7 is designated, the state of failure production is stored to the specific area, so that the information of the area is displayed to the display device 11.
COPYRIGHT: (C)1981,JPO&Japio
JP16444179A 1979-12-17 1979-12-17 Data recorder Pending JPS5687147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16444179A JPS5687147A (en) 1979-12-17 1979-12-17 Data recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16444179A JPS5687147A (en) 1979-12-17 1979-12-17 Data recorder

Publications (1)

Publication Number Publication Date
JPS5687147A true JPS5687147A (en) 1981-07-15

Family

ID=15793216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16444179A Pending JPS5687147A (en) 1979-12-17 1979-12-17 Data recorder

Country Status (1)

Country Link
JP (1) JPS5687147A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5894034U (en) * 1981-12-18 1983-06-25 株式会社山武 tracing device
JPS59158423A (en) * 1983-02-28 1984-09-07 Toshiba Corp Bus supervising device
JPS60201451A (en) * 1984-03-26 1985-10-11 Fujitsu Ltd System supervisory control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5894034U (en) * 1981-12-18 1983-06-25 株式会社山武 tracing device
JPS59158423A (en) * 1983-02-28 1984-09-07 Toshiba Corp Bus supervising device
JPS60201451A (en) * 1984-03-26 1985-10-11 Fujitsu Ltd System supervisory control system

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