JPS55157044A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55157044A
JPS55157044A JP6507079A JP6507079A JPS55157044A JP S55157044 A JPS55157044 A JP S55157044A JP 6507079 A JP6507079 A JP 6507079A JP 6507079 A JP6507079 A JP 6507079A JP S55157044 A JPS55157044 A JP S55157044A
Authority
JP
Japan
Prior art keywords
data
check bit
parity error
converter
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6507079A
Other languages
Japanese (ja)
Other versions
JPS6155696B2 (en
Inventor
Kazuhiro Iwata
Noboru Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6507079A priority Critical patent/JPS55157044A/en
Publication of JPS55157044A publication Critical patent/JPS55157044A/en
Publication of JPS6155696B2 publication Critical patent/JPS6155696B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable to leave the error career, even if parity error is present in write- in data, by providing a check bit generator, parity error detector and data check bit converter.
CONSTITUTION: A memory controller 6 includes a parity error detector 11, check bit generator 12 and data check bit converter 13. If the detector 11 detects no parity error relating to the data to be written in the memory 7, the check bit produced at the produce unit 12 and the data on a data line 14 become write-in data and check bit as they are without processig at the converter 13 and fed to the memory 7 on the signal line 18. On the other hand, if the parity error is detected 11, the parity error signal is outut to the converter 13 on the signal line 17, and the converter 13 converts the input data or check bit to obtain uncorrectable error and delivers it to the memory 7 via the signal line 18. That is, the presence of parity error can be left.
COPYRIGHT: (C)1980,JPO&Japio
JP6507079A 1979-05-28 1979-05-28 Information processor Granted JPS55157044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6507079A JPS55157044A (en) 1979-05-28 1979-05-28 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6507079A JPS55157044A (en) 1979-05-28 1979-05-28 Information processor

Publications (2)

Publication Number Publication Date
JPS55157044A true JPS55157044A (en) 1980-12-06
JPS6155696B2 JPS6155696B2 (en) 1986-11-28

Family

ID=13276312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6507079A Granted JPS55157044A (en) 1979-05-28 1979-05-28 Information processor

Country Status (1)

Country Link
JP (1) JPS55157044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4660068A (en) * 1982-08-24 1987-04-21 Nippon Telegraph & Telephone Corporation Substrate structure of semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4660068A (en) * 1982-08-24 1987-04-21 Nippon Telegraph & Telephone Corporation Substrate structure of semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS6155696B2 (en) 1986-11-28

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