JPS57153352A - Input and output instruction tracing system - Google Patents

Input and output instruction tracing system

Info

Publication number
JPS57153352A
JPS57153352A JP56038009A JP3800981A JPS57153352A JP S57153352 A JPS57153352 A JP S57153352A JP 56038009 A JP56038009 A JP 56038009A JP 3800981 A JP3800981 A JP 3800981A JP S57153352 A JPS57153352 A JP S57153352A
Authority
JP
Japan
Prior art keywords
input
output instruction
output
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56038009A
Other languages
Japanese (ja)
Inventor
Toshiharu Ogasawara
Yoshiyuki Yugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56038009A priority Critical patent/JPS57153352A/en
Publication of JPS57153352A publication Critical patent/JPS57153352A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Abstract

PURPOSE:To make a failure analysis easy, by storaging the input/output instruction trace information to an RAM incorporated in an input/output control mechanism, and surely obtaining a trace information for an input/output instruction. CONSTITUTION:To a central processing unit 1, a main storage 3 and an input/ output control mechanism 4 are connected via an interface bus 2. The input/output control mechanism 4 consists of an interface section 5 with the central processing unit 1, a microprocessor 6, a read only memory ROM8 storing a microprogram, a random access memory RAM7, and an interface section 10 with an input/output device 9, for mutual connection via a common bus 11. The interface section 5 with the central processing unit 1 is provided with an input/output instruction register 12 and a data register 13.
JP56038009A 1981-03-18 1981-03-18 Input and output instruction tracing system Pending JPS57153352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56038009A JPS57153352A (en) 1981-03-18 1981-03-18 Input and output instruction tracing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56038009A JPS57153352A (en) 1981-03-18 1981-03-18 Input and output instruction tracing system

Publications (1)

Publication Number Publication Date
JPS57153352A true JPS57153352A (en) 1982-09-21

Family

ID=12513570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56038009A Pending JPS57153352A (en) 1981-03-18 1981-03-18 Input and output instruction tracing system

Country Status (1)

Country Link
JP (1) JPS57153352A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6325742A (en) * 1986-07-18 1988-02-03 Nec Corp Microprocessor with tracing function
JPH0493694U (en) * 1990-12-28 1992-08-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6325742A (en) * 1986-07-18 1988-02-03 Nec Corp Microprocessor with tracing function
JPH0493694U (en) * 1990-12-28 1992-08-14

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