JPS6325742A - Microprocessor with tracing function - Google Patents

Abstract

PURPOSE:To easily obtain trace information without using an external device by tracing the operand data on an IO instruction to a main memory via a microprogram. CONSTITUTION:A microprocessor containing a tracing function consists of a prefetch unit (PFU)1, a memory control unit (MMU)2, a bus control unit (BCU)3, a microsequencer (muSEQ)4, a micro read-only memory (muROM)5, and an executing unit (EXU)6. When a trace control flip-flop set in the EXU6 is turned on by a program, such desired trace information as the data and channel data stored in a work register of the EXU6, an answer received from an IO device, the timer values of a program counter and the EXU6, etc., are written to a main memory.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprocessor with a trace function, and in particular a trace function that stores trace information in a memory area associated with the execution of input/output instructions (hereinafter abbreviated as IO instructions). The present invention relates to a microprocessor having m-capability.

[Conventional technology]

Conventionally, no microprocessor of this kind has a function to trace the actual bus dialog of 10 instructions to the external input/output device C of the microprocessor (hereinafter abbreviated as IO device), and therefore an alternative method has been proposed. As a result, bus tracing was performed using an external device such as an in-circuit emulator.

[Problem that the invention seeks to solve]

The conventional tracing means for microprocessors described above requires the use of an external device, so it is necessary to attach a special adapter to the socket of the microprocessor, and it is difficult to operate the system with the adapter attached. The disadvantage is that there are many restrictions such as the physical space required.

Furthermore, due to the above-mentioned restrictions, there is a drawback that tracing cannot be easily performed at the user's site when performing failure analysis.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor with trace R capability that can perform tracing up to the points mentioned above without using any external equipment.

[Means for solving problems]

A microprocessor with a trace function according to the present invention includes a trace information holding means for holding necessary information such as an operand of an input/output instruction and a response from an input/output device in a work register while executing an input/output instruction; a trace determination means that determines whether tracing is instructed by determining the state of a trace control flip-flop that is turned on and off by a program at the end of execution of an instruction; and this trace determination means determines that tracing is instructed. and trace execution means for tracing the input/output command by storing the necessary information held in the trace information holding means in a memory area when the input/output command is executed.

[Effect]

In the microprocessor with a trace function of the present invention, the trace information holding means holds necessary information such as operands of the input/output instruction and responses from the input/output device in the work register while executing the input/output instruction, and the trace judgment means determines whether tracing is instructed by determining the state of a trace control flip-flop that is turned on and off by the program at the end of execution of an input/output instruction, and the trace execution means determines whether tracing is instructed by the trace determination means. When it is determined that the input/output instruction is traced, the necessary information held in the trace information holding means is stored in the memory area.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a microprocessor with a trace function according to an embodiment of the present invention. , a memory management unit (hereinafter abbreviated as MMU) 2, a bus control unit (hereinafter abbreviated as BCU) 3, a micro sequencer (hereinafter abbreviated as μSEC) 4, and a micro read-only memory (hereinafter abbreviated as μSEC). (abbreviated as μROM)5
and an execution unit (hereinafter abbreviated as EXU) 6.

The PFUI prefetches instructions to be executed from main memory (not shown), decodes the instructions, generates effective operand addresses, and sends them to MMU2.

The MMU 2 is a unit that converts virtual addresses sent from each unit into real addresses.

The MMU 2 has a translation lookaside buffer (TLB) therein, and realizes high-speed address translation.

BCtJ3 is a unit that carries the real address sent from MMU2 onto an external bus and accesses the main memory and input/output devices.

μ5EQ4 is a microsequencer that generates a microprogram address based on instruction decode information f[a from the PFUI, accepts various interrupts, and reflects the address in the microprogram.

μROM5 is a ROM that stores a microprogram.

EXU6 is a unit that actually executes instructions, and its internal configuration includes registers and an arithmetic logic unit (ALU).
, barrel shifter, work registers used by the microprogram, and trace control flip-flops.

Referring to FIG. 1, the processing procedure of the input/output procedure (hereinafter abbreviated as IO procedure) in the microprocessor with trace function of this embodiment includes an operand data retrieval step 11, a channel data retrieval step 12, and a data sending step. The step 13 includes a step 13, a response receiving step 14, a trace on determination step 15, a trace information writing step 16, and a response storage step 17.

Next, the operation of the microprocessor with trace function of this embodiment configured as described above will be explained.

When the microprocessor executes an IO instruction, it fetches 10 instructions from the main memory, decodes them with PFU1, and sends the entry addresses of 10 procedures of the microprogram to μ5EQ4.

As a result, the ■0 procedure starts.

■ In the 0 procedure, ■ Take out the data that is the operand of the 0 instruction (step 11). This data is usually
These are various commands for the O device. This data is stored in one of the work registers within EXU6.

Next, channel data, which is one of the operands of the 10 instructions, is taken out (step 12), which corresponds to the address for specifying the 0 device.

This channel data is stored in one of the work registers.

Next, issue a microcommand to BCU3,
The aforementioned data and channel data are sent to an external bus (not shown) outside the chip of the microprocessor (step 13).

After this, the response from the 0 device is received via the BCU 3 (step 14). The response includes acceptance or rejection of the data of the 1o device, and unique status of the 0 device.

Then EXUs turned on and off by the program
Check the trace control flip-flop in 6 (
Step 15), ) If the race control flip-flop is on, the aforementioned data stored in the work register of EXU6, channel data, responses from 10 devices, program counter.

Write necessary trace information such as the timer value of EXU6 in the designated trace area on the main memory in the specified format (step 16).If the trace control flip-flop is not turned on in the judgment in step 15, the trace information is Writing to main memory is not performed.

After this, ■ store the response of the 0 device in the operand area, and
0 instruction ends (step 17).

〔Effect of the invention〕

As explained above, the present invention allows operand data of 10 instructions to be traced to the main memory by a microprogram that executes 0 instructions for 10 devices external to the microprocessor, thereby easily eliminating the need for external devices. This has the effect of being able to obtain trace information.

Furthermore, this has a great effect on software evaluation and maintenance as well as failure analysis due to hardware failure. In particular, in the case of (1) 0 instructions, the sequence of commands for 10 devices often has an important meaning, so the effect of tracing 10 instructions is large.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the processing procedure of an IO procedure executed in a microprocessor with a trace function according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the microprocessor with a trace function according to the embodiment. be. In the figure, l...Briefetch unit (PFU), 2...Memory management unit (MMU), 3...Bus control unit (BCU), 4...Micro sequencer (μ5EQ
), 5...Microphone t12ROM (#ROM), 6...
...Execution unit (EXU), 11...Operand data retrieval step, I2...
・Channel data extraction step, 13...Data sending step, 14...Response receiving step, 15...Trace on determination step, 16...Trace information writing step, 17...Response storage step.

Claims (1)

[Scope of Claims] Trace information holding means for holding necessary information such as operands of the input/output instruction and responses from the input/output device in a work register while the input/output instruction is being executed; trace determining means for determining whether tracing is instructed by determining the state of a trace control flip-flop that is turned on and off by a program; A microprocessor with a trace function, comprising: trace execution means for tracing the input/output instruction by storing the necessary information held in the trace information holding means in a memory area.