JP2013196241A - Information processor and log acquisition method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily determine the factor of memory breakdown.SOLUTION: A CPU interface 352 receives control information from a virtual CPU, and stores it in a monitor address leading register 353, a monitor size register 354, and a log output control flag register 355. A log output control circuit 356 receives memory access information from a virtual CPU, a virtual DMA (Direct Access Memory) controller and a virtual device, and when determining to output a log 401 in accordance with a control flag stored in the log output control flag register 355, acquires a monitor leading address and a monitor size from the monitor address leading register and the monitor size register, and when a write address included in the memory access information is included in a range (monitor area) of a value calculated by adding a monitor size to a monitor address from the monitor leading address, outputs the memory access information as the log 401.

Description

  The present invention relates to an information processing apparatus and a log acquisition method.

In program development, one of the obstacles that makes investigation and analysis longer is data modification due to illegal memory operations, so-called memory destruction.
In the case where the memory address to be monitored can be identified, it is possible to analyze by collecting and accumulating the action log focusing on that address, but in the case of memory that dynamically acquires and uses resources like a buffer, It is necessary to investigate all programs that cannot use memory addresses and use dynamically used memory resources. In addition, since there is a restriction on the log area, an investigation method is adopted in which the investigation target is narrowed down to one program and the operation check is repeated to collapse the cause.

  In a program that controls multiple processes, such as multi-processes and multi-threads, memory operations are performed by individual processes, so it may not be possible to identify the problem (failure) even if you follow the contents of a single thread. there were.

  In addition to the Central Processing Unit (CPU), there are devices that can perform memory operations, such as a Direct Memory Access (DMA) controller, so that the range to be investigated is widened and there is no effective means for identifying the cause.

JP 2007-199845 A JP 2007-272303 A

  In one aspect, an object of the present invention is to make it possible to easily determine the cause of memory corruption.

An information processing apparatus according to an embodiment includes a processing device and a memory including a virtual memory allocated to a virtual machine.
The processing apparatus includes a virtual processing unit, a virtual device unit, and a log output control unit.

The virtual processing unit executes a program, writes to the virtual memory, and outputs first memory access information related to writing to the virtual memory.
The virtual device unit receives a write command from the processing unit, writes to the virtual memory, and outputs second memory access information related to writing to the virtual memory.

  The log output control unit receives the first and second memory access information, and outputs the first and second memory access information as a log.

  According to the information processing apparatus of the embodiment, the cause of memory destruction can be easily determined.

It is a block diagram of the information processing apparatus which concerns on embodiment. It is a block diagram of the log output control part which concerns on embodiment. It is a figure which shows the example of a log. It is a figure which shows the library of an output control instruction | indication. It is a flowchart of processing of a virtual CPU. It is a flowchart of a process of a virtual DMA controller. It is a flowchart of a process of a virtual device. It is a flowchart of the process of the log output control part which concerns on embodiment. It is a block diagram of information processing apparatus (computer).

Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 is a configuration diagram of an information processing apparatus according to an embodiment.
The information processing apparatus 101 includes a host operating system (OS) 201 and a virtual machine 301.

The information processing apparatus 101 is a computer such as a personal computer, for example.
The host OS 201 is an OS installed in the information processing apparatus 101.

  The virtual machine 301 is a virtual computer that runs on the host OS 201, and is realized by software that emulates the computer. The virtual machine 301 is realized by reading and executing software that emulates a computer by a central processing unit (CPU) included in the information processing apparatus 101.

  The virtual machine 301 includes a virtual CPU 311, a virtual DMA controller 321, a virtual device 331, a virtual arbiter 341, a log output control unit 351, a virtual memory 361, and a virtual bus 371.

  The virtual CPU 311, virtual DMA controller 321, virtual device 331, virtual arbiter 341, log output control unit 351, and virtual memory 361 are connected via a virtual bus 371.

  The virtual CPU 311 reads out and executes the program from the virtual memory 361, and accesses (writes and reads) the virtual memory.

  The virtual CPU 311 outputs an access command to the virtual memory 361 to the virtual DMA controller 321 and the virtual device 331.

  The virtual CPU 311 outputs control information to the log output control unit 351. The control information includes a monitoring head address, a monitoring size, and a control flag.

  The virtual CPU 311 outputs information (memory access information) when writing to the virtual memory 361. The memory access information output from the virtual CPU 311 includes a program counter (PC) value, an instruction code, a write address, and write data when writing occurs.

The PC value is an address of a memory in which an instruction to be executed next by the virtual CPU 311 is stored.
The instruction code is an instruction code executed by the virtual CPU 311.

The write address is the address of the virtual memory 361 that is the write destination.
Write data is the value of the written data.

  The virtual DMA controller 321 receives an access command to the virtual memory 361 from the virtual CPU 311 and accesses (writes and reads) the virtual memory 361 without going through the virtual CPU 311. The virtual DMA controller 321 outputs information (memory access information) when writing to the virtual memory 361. The memory access information output by the virtual DMA controller 321 includes a write address, write data, data size, access source information, and source row number.

The write address is the address of the virtual memory 361 that is the write destination.
Write data is the value of the written data.
The data size is the size of the write data.

The access source information is information indicating the virtual DMA controller 321 such as a device name, for example.
The source line number is the line number of the program emulating the virtual DMA controller 321 executed at the time of writing to the virtual memory 361.

  The virtual device 331 is a peripheral device (for example, a serial advanced technology attachment (SATA) controller) included in the virtual machine 301. The virtual device 331 receives an access command to the virtual memory 361 from the virtual CPU 311 and accesses (writes and reads) the virtual memory 361 without going through the virtual CPU 311.

  The virtual device 331 outputs information when writing to the virtual memory 361 (memory access information).

  The memory access information output by the virtual device 331 includes a write address, write data, data size, access source information (for example, information indicating the virtual device 331 such as a device name), and a source line number.

The write address is the address of the virtual memory 361 that is the write destination.
Write data is the value of the written data.
The data size is the size of the write data.

The access source information is information indicating the virtual device 331 such as a device name, for example.
The source line number is the line number of the program emulating the virtual device 331 executed at the time of writing to the virtual memory 361.

  The virtual arbiter 341 performs permission control of writing to the virtual memory 361 for the virtual CPU 311, the virtual DMA controller 321, and the virtual device 311.

  The log output control unit 351 outputs the received memory access information as a log 401. The output log 401 is stored in, for example, a storage device included in the information processing apparatus, for example, a magnetic disk device or a semiconductor storage device. In addition, the contents of the log 401 are added to the previously output log.

  The log stored in the storage device included in the information processing apparatus 101 is displayed on a display device or the like included in the information processing apparatus 101 when the information processing apparatus 101 receives an output instruction.

  The virtual memory 361 is a virtual memory assigned to the virtual machine 301. The virtual memory 361 is a part of the (physical) memory included in the information processing apparatus 101.

FIG. 2 is a configuration diagram of a log output control unit according to the embodiment.
The log output control unit 351 includes a CPU interface 352, a monitoring address head register 353, a monitoring size register 354, a log output control flag register 355, and a log output control circuit 356.

  The CPU interface 352 receives control information from the virtual CPU 311. The control information includes a monitoring head address, a monitoring size, and a control flag.

  The monitoring address head register 353 stores the head address value (monitoring head address) of the area of the virtual memory 361 monitored by the log output control circuit 356.

  The monitor size register 354 stores size information (monitor size) of the area of the virtual memory 361 monitored by the log output control circuit 356.

  The log output control flag register 355 stores a control flag for controlling the operation of the log output control circuit 356.

  The log output control circuit 356 receives memory access information from the virtual CPU 311, the virtual DMA controller 321, and the virtual device 331.

  The log output control circuit 356 refers to the log output control flag register 355 and determines whether to output the log 401 according to the control flag stored in the log output control flag register 355. For example, when “1” is stored as a control flag in the log output control flag register 355, the log output control circuit 356 determines to output a log, and when “0” is stored, the log output control circuit 356. Determines that no log is output.

  When the log output control circuit 356 determines to output the log, the log output control circuit 356 refers to the monitoring address head register 353 and the monitoring size register 354 and acquires the monitoring head address and the monitoring size. The log output control circuit 356 determines whether or not the write address included in the memory access information is included in the range (monitoring area) of the value obtained by adding the monitoring size to the monitoring address from the monitoring head address. When the write address is included in the monitoring area, the memory access information is output as the log 401. When the monitoring head address and the monitoring size are NULL, that is, when the monitoring area is not designated, the log output control circuit 356 outputs the memory access information as the log 401.

FIG. 3 is a diagram illustrating an example of a log.
The access information received from the virtual CPU 311 is described in the first and second lines of the log 401 shown in FIG. 3, the access information received from the virtual DMA controller 321 is described in the third and fourth lines, and the fifth to seventh lines. Describes the access information received from the virtual device 331.

  In the first and second lines of the log 401, a program counter (PC) value, an instruction code, a write address, and write data are described. PC, op_code, addr, and val indicate a PC value, an instruction code, a write address, and write data, respectively.

  In lines 3 to 7 of the log 401, the write address, write data, data size, access source information, and source line number are described. addr, val, and len indicate a write address, write data, and a data size, respectively.

  Note that dev.c described as access source information indicates a virtual device 331, and dma.c indicates a virtual DMA controller 321.

  Next, a verification target program (program to be verified) executed by the virtual machine 301 will be described.

  The program to be verified includes an output control instruction for outputting control information to the log output control unit 351.

FIG. 4 is a diagram showing a library of output control instructions.
In the output control instruction (log_ctl), a monitoring head address (start_addr), a monitoring size (size), and a control flag (trace_flag) are given as arguments.

  The monitoring head address is the head address value of the area of the virtual memory 361 monitored by the log output control circuit 356.

The monitoring size is the size of the area of the virtual memory 361 monitored by the log output control circuit 356.
The control flag is a flag that controls the operation of the log output control circuit 356.

log_ctl performs the following three steps:
(1) Write the monitoring head address (start_addr) to the monitoring address head register 353 of the log output control unit 351.
(2) The monitoring size (size) is written in the monitoring size register 354 of the log output control unit 351.
(3) Write a control flag (trace_flag) to the log output control flag register 355 of the log output control unit 351.

  A log acquisition method according to the embodiment using the output control instruction (log_ctl) will be described. The user adds a function that calls log_ctl to the program to be verified.

  When the log output control circuit 356 wants to start outputting the log, that is, when the log output start instruction is to be given, “1” is given to the control flag of the argument of log_ctl.

When it is desired to end the log output to the log output control circuit 356, that is, when a log output end instruction is to be issued, “0” is given to the control flag of the argument of log_ctl.
The user describes a “log output start instruction” in advance before the start step of the investigation target portion (for example, the suspected portion of memory corruption) of the program to be verified.

  In addition, the user describes in advance a “log output end instruction” before the end step of the investigation target portion (for example, the suspected portion of memory destruction) of the program to be verified.

  In "Log output start instruction" and "Log output end instruction", the monitoring start address (start_addr) is given a variable that specifies the memory resource to be dynamically acquired and used, and the monitoring size (size) is the area to be monitored Give the size.

For example, when it is desired to execute “log output start instruction”, the following command is described before the start step of the investigation target portion of the program to be verified.
log_ctl (& variable, size, 1)

  “& Variable” indicates the monitoring start address, “size” indicates the monitoring size, and “1” indicates the control flag. “& Variable” indicates the head address of the area of the virtual memory 361 secured by the program to be verified.

In addition, when the area to be monitored cannot be specified, the user gives a “log output start instruction” to the program to be verified.
log_ctl (NULL, NULL, 1)
And write
As "log output end instruction"
log_ctl (NULL, NULL, 0)
Is described.

  Thus, by specifying NULL for the monitoring head address (start_addr) and the monitoring size (size), the log output control circuit 356 outputs all the received memory access information as the log 401.

Further, in the program to be verified, when it is desired that the log output control circuit 356 output a log for a memory area that has been dynamically secured and released using a function such as “malloc” or “free”, as follows: Add instructions to the program to be verified.
ptr = malloc (SIZE);
log_ctl (ptr, SIZE, 1)
...
...
log_ctl (ptr, SIZE, 0)
free (ptr)

  The above instruction will be described. First, an area having a size of “SIZE” is secured by malloc (SIZE), and a pointer indicating the head address of the area is stored in ptr.

  “Log output start instruction” is performed by log_ctl (ptr, SIZE, 1), and the log output control circuit 356 outputs memory access information for an area of SIZE from ptr as a log.

  “Log output end instruction” is performed by log_ctl (ptr, SIZE, 0), and the log output control circuit 356 stops outputting the memory access information for the area of SIZE from ptr.

The area indicated by ptr is released by free (ptr).
By describing the output control instruction (log_ctl) in the program to be verified as described above, it is possible to monitor the dynamically secured area.

FIG. 5A is a flowchart of processing of the virtual CPU.
The virtual CPU 311 reads an instruction described in the program to be verified and executes the instruction (step S601). Examples of the instruction include the above-described output control instruction, data writing to the virtual memory 361, and an instruction to access the virtual memory 361 to the virtual DMA controller 321 or the virtual device 331. The virtual CPU 311 outputs memory access information when writing to the virtual memory 361.

  The virtual CPU 311 performs interrupt processing and the like (step S602), and performs dispatch processing (step S603).

FIG. 5B is a flowchart of processing of the virtual DMA controller.
The virtual DMA controller 321 receives an access command to the virtual memory 361 from the virtual CPU 311, reads data from the transfer source virtual memory 361, and writes the data to the transfer destination virtual memory 361. The virtual DMA controller 321 outputs memory access information when writing to the virtual memory 361. The virtual DMA controller 321 performs an interrupt process or the like (step S611).

FIG. 5C is a flowchart of virtual device processing.
The virtual device 331 receives an access command to the virtual memory 361 from the virtual CPU 311, writes data to the destination virtual memory 361, and performs an interrupt process or the like (step S 621). The virtual device 331 outputs memory access information when writing to the virtual memory 361.

FIG. 6 is a flowchart of processing of the log output control unit according to the embodiment.
In step S <b> 501, the log output control circuit 356 receives memory access information from the virtual CPU 311, the virtual DMA controller 321, or the virtual device 311.

  In step S502, the log output control circuit 356 checks whether or not the control flag stored in the log output control flag 355 is “1”. If the control flag is “1”, the control proceeds to step S503, and if the control flag is “0”, the control returns to step S501. When the control flag is “0”, the log output control circuit 356 discards the received access information.

  In step S503, the log output control circuit 356 refers to the write address included in the memory access information.

  In step S504, the log output control circuit 356 refers to the monitoring address head register 353 and the monitoring size register 354, and acquires the monitoring head address and the monitoring size. Then, the log output control circuit 356 determines whether or not the write address included in the memory access information is included in the range (monitoring area) of the value obtained by adding the monitoring size to the monitoring address from the monitoring head address.

  If the write address is included in the monitoring area, control proceeds to step S505, and if the write address is outside the monitoring area, control returns to step S501. If the monitoring head address and the monitoring size are NULL, that is, if the monitoring area is not specified, the control proceeds to step S505.

  In step S505, the log output control circuit 356 outputs the memory access information as the log 401.

  According to the information processing apparatus of the embodiment, all devices (CPU, DMA controller, etc.) that access the memory are traced and output to one log file. The user can easily determine the destruction source by verifying the log file, and the failure analysis time can be shortened.

  According to the information processing apparatus of the embodiment, the size of the log output by the log output control unit is reduced by limiting the monitoring area of the virtual memory with the control information to the log output control unit. In addition, since the processing of the log output control unit is limited, there is an effect that the load on the information processing apparatus 101 is reduced and the emulation time is not greatly increased.

FIG. 7 is a configuration diagram of the information processing apparatus (computer).
The information processing apparatus 101 according to the embodiment is realized by an information processing apparatus 1 as illustrated in FIG. 7, for example.

  The information processing apparatus 1 includes a CPU 2, a memory 3, an input unit 4, an output unit 5, a storage unit 6, a recording medium drive unit 7, and a network connection unit 8, which are connected to each other by a bus 9.

  The CPU 2 is a central processing unit that controls the entire information processing apparatus 1. The CPU 2 corresponds to the virtual CPU 311, the virtual DMA controller 321, the virtual device 331, the virtual arbiter 341, and the log output control unit 351.

  The memory 3 is a Read Only Memory (ROM) or Random Access Memory (RAM) that temporarily stores a program or data stored in the storage unit 6 (or the portable recording medium 10) during program execution. It is memory. The CPU 2 executes the various processes described above by executing a program using the memory 3.

  In this case, the program code itself read from the portable recording medium 10 or the like realizes the functions of the embodiment.

The input unit 4 is, for example, a keyboard, a mouse, a touch panel, or the like.
The output unit 5 is, for example, a display, a printer, or the like.
The storage unit 6 is, for example, a magnetic disk device, an optical disk device, a tape device, or the like. The information processing apparatus 1 stores the above-described program and data in the storage unit 6 and reads them into the memory 3 and uses them as necessary.

The memory 3 includes an area of the virtual memory 361.
The recording medium driving unit 7 drives the portable recording medium 10 and accesses the recorded contents. As the portable recording medium, any computer-readable recording medium such as a memory card, a flexible disk, a compact disk read only memory (CD-ROM), an optical disk, and a magneto-optical disk is used. The user stores the above-described program and data in the portable recording medium 10 and reads them into the memory 3 and uses them as necessary.

  The network connection unit 8 is connected to an arbitrary communication network such as a LAN, and performs data conversion accompanying communication.

101 Information processing apparatus 201 Host OS
301 virtual machine 311 virtual CPU
321 Virtual DMA
331 Virtual device 341 Virtual arbiter 351 Log output control unit 352 CPU interface 353 Monitor address start register 354 Monitor size register 355 Log output control flag register 356 Log output control circuit 361 Virtual memory 371 Virtual bus

Claims (6)

An information processing apparatus comprising: a processing device; and a memory including a virtual memory allocated to a virtual machine,
The processor is
A virtual processing unit that executes a program, writes to the virtual memory, and outputs first memory access information related to writing to the virtual memory;
A virtual device unit that receives a write command from the virtual processing unit, writes to the virtual memory, and outputs second memory access information related to writing to the virtual memory;
A log output control unit that receives the first and second memory access information and outputs the first and second memory access information as a log;
An information processing apparatus comprising: The first and second memory access information includes a write address for writing to the virtual memory,
The virtual processing unit outputs area information indicating a virtual memory area monitored by the log output control unit,
The log output control unit stores the area information, and outputs the first and second memory access information when the write address is within an area indicated by the area information. Item 6. The information processing apparatus according to Item 1.   The information processing apparatus according to claim 1, wherein the virtual processing unit outputs information indicating an area dynamically secured by the program as the area information. The first memory access information further includes a program counter value, an instruction code, and write data,
The information processing apparatus according to claim 2, wherein the second memory access information further includes information indicating write data, a size of the write data, and the virtual device. A log acquisition method executed by an information processing apparatus including a memory including a virtual memory allocated to a virtual machine,
Executing a program, writing to the virtual memory, outputting first memory access information relating to writing to the virtual memory;
Writing to the virtual memory, and outputting second memory access information related to writing to the virtual memory;
A log acquisition method comprising: receiving the first and second memory access information and outputting the first and second memory access information as a log. The first and second memory access information includes a write address for writing to the virtual memory,
In the process of outputting the first and second memory access information as a log, referring to area information indicating a virtual memory area to be monitored, and when the write address is within the area indicated by the area information, 6. The log acquisition method according to claim 5, wherein the first and second memory access information are output.

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