JPS6321157A - Printer controller - Google Patents

Abstract

PURPOSE:To enable a set of two MPUs to divide the work among them without considering each other the information and speed in processing of a counterpart, by a method wherein; memory addresses subjected to the access of the set of two MPUs are compared with each other, or alternatively the memory address subjected to the access of at least one of the MPUs is compared with the value stored in a register and according to the result a memory operation of at least one of the MPUs is controlled. CONSTITUTION:As soon as an MPU 11 writes data in a memory 14, an MPU 12 processes the data. If the processing speed of the MPU 12 higher than that of the MPU 11, the MPU 12 is controlled by an address competitive control part 15 so as not to exceed the MPU 11 on the address of a memory 14; therefore, both the hosts may continue normal operations without considering each other. Additionally, the address competitive control part 15 can previously store the address in the memory area for storing the data which is not desired to be processed in the MPU 12 in an address bus register to compare the memory address subjected to the access of the MPU 12 with the address stored in the address bus register; according to the result of the comparison it can inhibit the MPU 12 from processing the data in the memory area.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a printer controller.

(Prior art) Conventional printer controllers have dual (DυA
L) A device with boat functions is being considered. This dual port function is used when two MPUs connected to two ports share memory.
It was difficult to perform the shared work of manipulating data and having the first MPU process the data in parallel. In other words, if the second MPU is faster than the first MPU, the second MPIJ will jump over the memory area being operated by the first MPtl (in other words, it will be ahead of the first MPU in terms of address). ) There is a risk that the unprocessed data of the first MPU will also be processed before or after the procedure, and it is necessary to make time adjustments depending on the combination of the two MPUs and the content of the processing operation. Also, if you do not want the data in a memory area of the first MPU to be processed by the second MPU, the second MPU cannot determine the memory area, so changes such as address calculation must be made by rewriting the software. I had no choice but to respond.

As a result, the operation efficiency of the dual port function is very poor1.
This required troublesome time adjustments or software changes.

(Objective) The present invention improves the above-mentioned drawbacks and provides dual-port connection.
It is an object of the present invention to provide a printer controller 'r1M in which two sets of 'IIPUs can perform multiple tasks without considering the processing content and speed of the other party.

(Also developed) As shown in FIG. 1, the present invention has a memory 3 shared by two sets of MPUs 1 and 2 connected to a dual port.

The control means 4 compares the memory addresses accessed by the MPUs 1 and 2 with each other or
The memory address accessed by at least one of tJl, 2 is compared with the value stored in the register, and the memory operation of at least one of the MPUs is controlled based on the comparison result.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, this embodiment has a dual port function, and two sets of MPIJs 11, 12 are connected to the dual port of this embodiment. This MPU 1
1.12 shares memory 13 and transfers data to control unit 1
3, the memo is stored in the memo Raigetsu 4, processed, and output to a printer for image recording.呵pu is for example ITi
If processing such as scaling is performed after all edge data has been written to the memory, one MPU will be in an idle state even if there is a dual port function, so in this example, the MPU II has just damaged the memory 14. The MPU 12 immediately processes the data. Even if the processing speed of the MPU 12 is faster than the processing speed of the MPUII, the MPulL2 is the address conflict controller 1.
5, on the address of the memory 14, the MPU t t
Therefore, both hosts do not have to consider each other's needs and can just continue normal operations.6 For example, as shown in FIG. 3, MPU 11
IF? stores data from address X to address Y in memory? ! When the liver gate 2 reduces the data due to the complexity, the address conflict control unit 15 compares the addresses accessed by the liver gates 1 and 12, and if the address Ntl on the old 2 side overtakes the address IIIA on the MPU II side, In other words, if NA>NB is checked and NA>NB is no longer true, a signal is given to adjust the time (make the user wait). In this way, various data processing tasks performed by the MPU 12, not just image scaling, are performed by the MPU 12. i, the image data is output at almost the same speed as when it is simply written into the memory 14.

In addition, the address conflict control unit 15 stores the address of the memory area in which data that is not desired to be processed by the main gate 2 is stored in the address bus register a, and sets the memory address accessed by the MpUt 2 to the address bus register. Compare it with the register address and use the result as MPL! +2
Data processing in the above memory area can be prohibited. In this way, the MPU 2 can be run normally without having to provide software with functions such as address calculation.

In this ':X example, address conflict control is performed as described above, so the MPU controls processing speed and processing data area.

This eliminates the need for troublesome adjustments and calculations such as start timing, and greatly reduces the need for software changes.

Figure 4 shows MPUII from address P to Q of memo 17111.
P is stored in the register 16 and Q is stored in the register 17, which shows an example of the address conflict control unit 15 when the data up to the address is not to be processed by the MPU I 2. The values P and Q of this register 16.17 are comparators (LS85) 18 to 274: TE MPU12 (7) 7
Do L//1. The address signals S from the buses are compared to determine whether Pus or S<Q, and the output thereof is input to the NOR circuit 28, and the output signal of the NOR circuit $328 is set to P≦SS.
At the time of Q, an interrupt (outputted to MPulL2 as No. 3).

The MPUI 2 processes the data in the memory 14 in order from the lowest address.

PH! When addressing the \ location, processing is interrupted by an interrupt signal from the NOR circuit 28, the value Q of the register 17 is read, and then data processing is resumed from address Q+1. Note that when the address conflict control section 15 simply prohibits the address conflict between the old 1 and 12, there is no need to provide a register, and it is sufficient to simply compare the signals from the address buses of MPUL and 12 using a comparison circuit.

(Effects) As described above, according to the present invention, when two sets of MPUs access memory shared by each other, the addresses are compared with each other, or the memory address accessed by at least one MPU is compared with the value of a register. Since the address operation of at least one of the MPUs is controlled based on the result, the two sets of MPUs can perform shared tasks without considering each other's processing content and speed, and can perform data input, data processing, and data output. A series of operations can be performed in a short time by making full use of the dual port function.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a flowchart of the embodiment, and Fig. 4 shows an example of an address conflict control section. It is a block diagram. 3...Memory, 4...Control means. Figure 1, 2nd flash ■ Procedural amendment (method) October 22, 1986

Claims (1)

[Claims] Compare the memory shared by two sets of microprocessing units (MPUs) connected to the dual port and the memory addresses accessed by the two sets of MPUs when the two sets of MPUs access this memory, or A printer controller comprising control means for comparing a memory address accessed by at least one of the MPUs with a value stored in a register and controlling memory operations of at least one of the MPUs based on the comparison result.