JPH0556544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer memory control method for a multiprocessor system.

[Conventional technology]

A conventional multiprocessor system consists of processors with the same performance and functionality, and when another processor performs a store operation, it receives a store address, checks whether the address is registered in the buffer memory of its own processor, and checks if the address is registered. When a multiprocessor system is in use, the uniqueness of data in a multiprocessor system is guaranteed by invalidating the buffer memory entry corresponding to the address (for example, Japanese Patent Laid-Open No. 116145/1983).

[Problem that the invention seeks to solve]

The conventional multiprocessor system mentioned above is
Since the performance was the same, we were able to exchange store addresses and invalidate the buffer memory, but
In a multiprocessor system composed of processors with different performance, there is a problem that, for example, a processor with low performance receives all store addresses for a store operation performed by a processor with high performance, making it impossible to invalidate the buffer memory. Even if you buffer the store address from a high-performance processor, you can only invalidate the buffer memory at a fraction of the speed, and when the store address buffer overflows and there is a possibility that it will overflow again, This is because if the store operation of a high-performance processor is stopped to prevent the store address buffer from overflowing, the high-performance processor will not be able to demonstrate its original performance.

[Means for solving problems]

An information processing apparatus having a buffer memory according to the present invention includes a boundary address holding means for holding a boundary address, a buffer memory address means for giving a buffer memory address, and a buffer memory for sequentially updating the contents of the buffer address means. address comparing means for comparing the address read from the address array of the buffer memory designated by the address update means and the buffer memory address means with the contents of the boundary address holding means;
and means for invalidating the buffer memory by the output of the address comparison means indicating that the address read from the address array exceeds the boundary address.

[Effect]

Since the low-speed processor (information processing device) invalidates the buffer memory only for the entry of the address exceeding the boundary address, the functions of the high-speed processor are not inhibited.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus having a buffer memory according to the present invention.

The buffer memory is composed of an address array 1 and a data array 2. address array 1,
In addition to the address register 12 that holds addresses to the data array 2, a boundary address register 3 that holds boundary addresses is provided. Address register 4 for buffer memory address array 1 and buffer memory data array 2; An address selection circuit 9 for outputting an address is provided,
An address data selection circuit 11 is provided for selecting the address data register 10, the upper part of the address register 12, and the boundary address register 3 for the address array 1, and outputting the selected data to the address data register 10. Address comparison circuit 6 compares the address read from buffer memory address array 1 with the address of address data register 10. Data register 8 holds data read from data array 2 in response to a match signal from address comparison circuit 6, and holds data read from main memory when no match signal is output. When a signal indicating that the address read from the address array 1 is larger than the address in the address data register 10 is output from the address comparison circuit 6, the buffer memory invalidation circuit 7 invalidates the entry of the address in the address array 1. do.

Next, the operation of this embodiment will be explained.

Normal read/write based on the contents of address register 12.
When a request is issued, the address is divided into upper and lower parts, and each address data selection circuit 1
1. Selected by address selection circuit 9 and set in address data register 10 and address register 4. Address array 1 and data array 2 of the buffer memory are read out according to the contents of address register 4, respectively. The data read from address array 1 is stored in address data register 1.
It is compared with the contents of 0 by the address comparison circuit 6. If the comparison results match, data array 2
The data read from is set in data register 8. If they do not match, the requested data is not in the buffer memory and is read from the main memory. The data read from the main memory is set in the data register 8 and also written to the data array 2. At that time, the contents of the address data register 10 are also written to the address array 1.

On the other hand, a buffer memory invalidation request is made when a process is moved by a procedure call or the like. In this case, the contents of the boundary address register 3 are selected by the address data selection circuit 11 and set in the address data register 10,
Address register 4 is reset. Then, the address selection circuit 9 controls the address update circuit 5 to be selected. The address register 4 is sequentially updated by +1 by the address update circuit 5.
Address array 1 outputs the contents specified by address register 4. The address comparison circuit 6 compares the output with the boundary address stored in the address data register 10, and if an address larger than the boundary address is detected, the buffer memory invalidation circuit 7 invalidates the entry. When all entries are processed by the address update circuit 5, invalidation ends. Whether to invalidate an address larger than the boundary address or an address smaller than the boundary address is switched depending on the type of invalidation request.

Although this embodiment shows a buffer memory having a one-compartment configuration, the present invention can be similarly applied to a multiple-compartment configuration. Further, in this embodiment, the boundary address register 3 is provided exclusively, but the address data register 10 is used as a boundary address holding means, and the boundary address register 3
A configuration without the is also possible. In this case, at the start of the buffer memory invalidation processing, a boundary address is set in the address data register 10 by a microprogram or the like.

FIG. 2 is a block diagram showing the configuration of a multiprocessor system embodying the present invention. The first main memory 21 is mainly used by the first arithmetic processor 25 . The first arithmetic processor 25 is
This is a low-speed, high-performance processor having the buffer memory 27 of the present invention shown in FIG. The second main memory 22 is mainly used by the second arithmetic processor 26. The second arithmetic processor 26 is a high-speed, low-performance processor. The first arithmetic processor 25 mainly uses the first main memory 21, but can also normally access the main memory 22 of another system from the first system control device 23 via the second system control device 24. I can do it. There is no buffer memory matching processing mechanism for store requests between the first arithmetic processor 25 and the second processor 26. This is because the processing speed of the second arithmetic processor 26 is several times faster than that of the first arithmetic processor 25, so even if the store address is sent from the second arithmetic processor 26 to the first arithmetic processor 25, it cannot be processed completely. This is because the high-speed processing capability of the second arithmetic processor 26 will be reduced. In the embodiment shown in FIG. 2, even if the second arithmetic processor 26 stores data in the main memory, a buffer memory invalidation request is not sent to the first arithmetic processor 25, and the process control is transferred from the second arithmetic processor 26 to the first arithmetic processor 25. When moving to the arithmetic processor 25, only the entry corresponding to the second storage section 22 of the buffer memory 27 is cleared. In other words, by controlling the boundary address explained in FIG. 1 to indicate the boundary between the first main memory 21 and the second main memory 22, Only entries corresponding to can be invalidated. The second arithmetic processor 26 does not access the first main memory 21. The first arithmetic processor 25 stores the first and second main memories 21 and 22.
access. Conventional buffer memory matching processing is performed between the input/output processor 28 and the first processor 25. In other words, the first processor 25
The buffer memory 27 is provided with a prior art invalidating means, which is the invalidating means shown in FIG.

〔Effect of the invention〕

As explained above, the present invention provides a boundary address holding means for holding a boundary address, and invalidates only the buffer memory entry corresponding to a specific main memory that exceeds the boundary address. It becomes possible to build a multiprocessor system,
This has the effect of making it possible to provide a system that takes advantage of the high speed and high functionality of each processor as a multiprocessor system as a whole.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing only the main parts of an embodiment of the information processing apparatus of the present invention, and FIG. 2 is a block diagram of a multiprocessor system including a processor having the buffer memory shown in FIG. 1... Buffer memory address array, 2...
Buffer memory data array, 3...Boundary address register, 4...Address register, 5...Address update circuit, 6...Address comparison circuit, 7...
... Buffer memory invalidation circuit, 8 ... Data register, 9 ... Address selection circuit, 10 ... Address data register, 11 ... Address data selection circuit, 12 ... Address register, 21 ... First
main memory, 22... second main memory, 23... first
system control device, 24... second system control device, 25... first arithmetic processor, 26...
. . . second arithmetic processor, 27 . . . buffer memory, 28 . . . input/output processor.

Claims (1)

[Scope of Claims] 1. A processor device having a buffer memory constituting a multiprocessor system, comprising: boundary address holding means for holding a boundary address; buffer memory address means for providing a buffer memory address; buffer memory address update means for sequentially updating the contents of the address means; and address comparison for comparing the address read from the address array of the buffer memory instructed by the buffer memory address means with the contents of the boundary address holding means. and means for invalidating all or only the corresponding entry in the buffer memory by the output of the address comparing means indicating that the address read from the address array exceeds a boundary address. Processor device.