JPH02156355A - Information processor - Google Patents

Abstract

PURPOSE:To improve the hit rate of a cache memory and to guarantee data without fail by making only the data in another memory device, excepting for the data in its own memory device existing in the cache memory ineffective. CONSTITUTION:When the ineffective request of the data in the cache memory to correspond to the address of the other memory device is outputted from an instruction control part 2 to a cache control circuit 12, the activation instruction of the ineffectiveness is executed to a cache ineffective control circuit 15 by the circuit 12. The circuit 15 executes the clear instruction of a directory AA 6 index address part in an absolute address register PAR 5 and executes the 0 address index of the AA 6. The index address part of an attribute display circuit AM 13 for 0-address entry read out of the AA 6 is set to a register 14. The index of the AM 13 is executed according to the address and it is decided by the circuit 15 whether the address registered to the 0-address of the AA 6 is the address to belong to its own memory device or the other memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly to data guarantee control of a cache memory in a processor between dedicated processors in an information processing apparatus having a multiprocessor configuration.

1m When a memory device connected to another processor is accessed and data is rewritten, if a copy of the corresponding data is stored in the cache memory within the own processor, the data rewriting will be performed by the own processor. The data will not be reflected in the internal cache memory, and the data will no longer be guaranteed.

Therefore, in the conventional method, data is guaranteed by controlling the clearing of all entries in the cache memory within the processor itself.

In this way, conventional data guarantee for the cache memory within a processor is achieved by clearing all entries in the cache memory within the processor itself when accessing another memory device connected to another processor.
This also clears the copy of the data in the own memory device connected to the own processor. Therefore, when accessing the own memory device after accessing another memory device, the own cache memory cannot be accessed and the own memory device must be accessed again, which increases access time and reduces system performance. have.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to improve the hit ratio of cache memory to own memory device access, An object of the present invention is to provide an information processing device that ensures data guarantee.

According to the present invention, the present invention includes a plurality of processors each having a cache memory storing a copy of a portion of data in a memory device, and accesses a memory device connected to a partner processor via inter-processor communication. An information processing apparatus comprising an access means for accessing another memory device connected to another processor from the own processor, and a memory address registered in a cache memory within the own processor in response to the access. The present invention is characterized by comprising a determination means for determining whether an address belongs to another memory device, and an invalidation control means for invalidating a cache directory within the own processor corresponding to an entry belonging to the other memory device based on the determination result. An information processing device is obtained.

Further, according to the present invention, information is provided that includes a plurality of processors each having a cache memory storing a copy of a portion of data in a memory device, and accesses information to a memory device connected to a partner processor via inter-processor communication. In a processing device, an access means for accessing another memory device connected to another processor from the own processor, and determining whether a registered address belongs to another memory device when registering data to a cache memory in the own processor. and attribute display means for displaying whether the address belongs to the own memory device or another memory device in the corresponding entry of the cache directory indicating the registered address of the cache memory, according to the result of this determination; An information processing apparatus is obtained, comprising: invalidation control means for searching the attribute display means of a cache directory and invalidating a cache directory within the own processor corresponding to an entry belonging to another memory device.

Fire scorch Next, the present invention will be explained with reference to the drawings.

First, referring to FIG. 2, it is a diagram showing the configuration of an information processing system to which the present invention is applied. EPUa21 and EPUb
22 are processors, EPUa 21 is a high-speed calculation processor, and EPUb 22 is a low-speed control processor. These processors are provided with cache units a and b, respectively.

5CUa23 and 5CUb24 are each a system control device, and MMa25 and MMb26 are each a memory device.

The operation of the system will be briefly explained with reference to FIG. The EPUb22 is a processor that controls the entire system, and when high-speed calculation is required, the EPUb22 is sent to MMA via paths 27→28→29 in order to start the high-speed calculation processor 21.
The job is stored at 25, and then from 27 to 28-30.
An instruction to start the job is given to the EPUa 21 via the . When the EPUa21 receives the startup instruction and becomes executable, it passes the path 30.
and 29, the job in the MMa 25 is executed using the cache a, and when the job execution is completed, a completion report is sent to the EPUb 22 via the path 30→28→27.

The EPUb 22, which has received the termination instruction, accesses the MMa 25 via paths 27→28→29 to obtain the execution results, and if necessary, stores the execution results in the MMb 26 via the paths 27→31. At this time, the EPU b 22 speeds up the processing while using the cache b.

Next, data guarantee control of cache b and MMa 25 in EPU b 22, which is the main focus of the present invention, will be explained with reference to FIG. FIG. 1 is a system block diagram of an embodiment of the present invention, and is a circuit block diagram for cache invalidation.

The instruction control unit 1.2 is an interface between the cache invalidation circuit and the cache memory unit, 1 is an interface for cache access addresses, and 2 is an interface related to cache memory invalidation control.

LAR3 is a register that holds the cache memory access logical address, and this logical address is TLB4.
The address is converted into an absolute address by the address and set in the absolute address register (PAR) 5.

AA6 is a directory indicating the registered address of the cache memory, and DA7 is a data array that holds data of the cache memory. CMP8 is a circuit that detects whether or not desired data exists in the cache memory by matching the address parts of absolute address register 5 and AA6. The result of the AND circuit 9 between this coincidence detection output and the valid display V of the address section of AA6 is sent to the flip-flop 1.
It is set to 0 to determine a cache hit (data in cache) or a cache miss (no data in cache).

The data read from DA7 is held in the register 11, and is returned to the cache access request source when the cache control circuit 12 determines that the data is cache hit based on the output of the flip-flop 10.

AM13 Self-memo Self-installed memory device This is an attribute display circuit that shows which memory device an accessible address including a memory device belongs to. is logically divided into two or more parts, and the address allocation of the memory can be made floating.Therefore, in the case of two divisions, it is 1 bit, and in the case of four divisions, it is 2 bits). indexed by register 14.

Cache invalidation control circuit 15 is cache control circuit 1
This circuit receives the activation of cache invalidation from PAR5, and controls the invalidation by setting the V bit clear register 17 of AA6 while counting up the index address part of AA6 in PAR5 with a counter 16.

Furthermore, a cache invalidation method will be explained in detail.

The TLB and cache memory are common, and their explanations will be omitted here. First, when the instruction control unit 2 issues a request to invalidate data in the cache memory corresponding to an address of another memory device to the cache control circuit 12, an instruction to start invalidation is issued to the cache invalidation control circuit 15. This is done by circuit 12.

Next, the cache invalidation control circuit 15 selects the AA of PAR5.
A of the 0 address entry read from AA6, which instructs to clear the 6 index address field and performs the 0 address index of AA6.
The index address field of M13 is set in the register 14.

AM13 is indexed using this address, and cache invalidation control circuit 15 determines whether the address registered at address O of AA6 belongs to the own memory device or another memory device.

The determined result is the own memory device r! (In other words, the data existing in DA7 of the cache memory is correct), the cache invalidation process corresponding to address 0 of AA6 ends. Also, if the determined result is an address of another memory device (that is, data must be guaranteed so that rewriting of the other memory device as a result of processing by another processor is not reflected in the cache memory of the own processor), the v bit clear register of AA6 17 is set to "0", the V bit portion of the corresponding address 0" of AA6 is set to "0", and the cache invalidation process is completed.

With the above processing, the cache invalidation processing corresponding to address O of AA6 is completed, and the same processing is performed at AA6.
will be repeated for the number of entries. When this is repeated, the index address section of AA6 of PAR5 is
This is done while counting up.

FIG. 3 is a system block diagram of another embodiment of the present invention. In FIG. 1, parts equivalent to those in FIG. 1 are indicated by the same reference numerals. is an attribute display circuit indicating which memory device it belongs to, and is indexed by the upper bits of the address of PAR5. The flip-flop 14 holds whether the corresponding data is the address of its own memory device or the address of another memory device when data is registered in the cache memory, and is registered as an attribute display bit in the corresponding entry of AA6.

Cache invalidation control circuit 15 is cache control circuit 1
This circuit receives the activation of cache invalidation from PAR5, and controls the invalidation by setting the V bit clear register 17 of AA6 while counting up the index address part of AA6 in PAR5 with a counter 16.

Furthermore, the cache invalidation method will be explained in detail.

First, when the instruction control unit 2 issues a request to invalidate data in the cache memory corresponding to an address of another memory device to the cache control circuit 12, an instruction to start invalidation is issued to the cache invalidation control circuit. 1
2.

Next, the cache invalidation control circuit 15 selects the AA of PAR5.
The address registered at address 0 of AA6 is specified by the attribute display bit (copy 0) of the address 0 entry read from AA6. Cache invalidation control circuit 1 determines whether the address belongs to the own memory device or another memory device.
Judge with 5.

If the determined result is an address of the own memory device (that is, the data existing in DA7 of the cache memory is correct), the cache invalidation process corresponding to address 0 of AA6 ends. Also, if the determined result is an address of another memory device (that is, data must be guaranteed so that rewriting of the other memory device as a result of processing by another processor is not reflected in the cache memory of the own processor), clear the V bit of AA6. 0'' is set in the register 17, and the V bit portion of ``0''0'' of the corresponding AA6 is set to ``0'', thereby terminating the cache invalidation process.

This completes the cache invalidation process corresponding to address O of AA6, and the same process is repeated for the number of entries in AA6. When repeating, the index address part of AA6 of PAR5 is counted up by the counter 16.

As described above, according to the present invention, data inconsistency caused by memory rewriting from another processor to data existing in the cache memory in the processor in a multiprocessor can be corrected by rewriting the cache memory when accessing another memory device. By invalidating only the data in the other memory device excluding the data in the own memory device existing in the memory device, there is an effect of improving the hit ratio of the cache memory with respect to the access to the own memory device after accessing the other memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an information processing system to which the embodiment of the present invention is applied, and FIG. 3 is a block diagram of another embodiment of the present invention. . Explanation of the symbols of the main parts 6... Cache address directory lift...
... Cache data array 8 ... Comparator 12 ... Cache control circuit 13 ... Memory attribute display circuit 15 ... Cache invalidation control circuit 16 ...
···counter

Claims (2)

[Claims] (1) An information processing device that includes a plurality of processors each having a cache memory storing a copy of a portion of data in a memory device, and that accesses a memory device connected to a partner processor via inter-processor communication. , an access means for accessing another memory device connected to another processor from the own processor, and in response to this access, reads a memory address registered in a cache memory in the own processor, and this address belongs to the other memory device. 1. An information processing device comprising: determination means for determining whether the address is an address; and invalidation control means for invalidating a cache directory within its own processor corresponding to an entry belonging to another memory device based on the determination result. (2) An information processing device that includes a plurality of processors each having a cache memory storing a copy of a portion of data in the memory device, and that accesses a memory device that is connected to a partner processor via inter-processor communication. , an access means for accessing another memory device connected to another processor from the own processor, and a determining means for determining whether a registered address belongs to another memory device when registering data in a cache memory in the own processor; Attribute display means for displaying whether the address belongs to the own memory device or another memory device in the corresponding entry of the cache directory indicating the registered address of the cache memory according to the determination result, and the attribute of the cache directory. An information processing apparatus comprising: invalidation control means for searching a display means and invalidating a cache directory within the own processor corresponding to an entry belonging to another memory device.