JP2759952B2 - Cache memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a cache memory, and in particular, when a CPU access to a cache memory does not hit, an access address of the CPU and a tag address of the cache memory. And a cache memory (hereinafter simply referred to as a cache) that determines whether to update the storage content of the cache memory based on the result.
It is about.

(Prior Art) In order to increase the processing speed of instructions in a data processing device, a part of the storage content of a main storage device is copied to a cache provided inside a CPU, and most of memory references are made to this cache. A method of doing so is used.

FIG. 5 is a block diagram of the data processing system having a cache. In the figure, CPU 1 is address bus 2
And the data bus 3 accesses the main storage device 4 and the cache 5 connected to the buses 2 and 3.

When the CPU 1 accesses the main storage device 4 and the cache 5 via the buses 2 and 3, the CPU 1 outputs a memory access signal 6 to the cache 5. When the address specified by the access signal matches the tag address of the cache 5 (hit), the cache 5 outputs data to the data bus 2 and activates the acknowledge signal 7 to notify the CPU 1 of access completion.

On the other hand, when the data requested by the access from the CPU 1 is not in the cache 5 (miss hit), the cache 5 outputs an operation signal 8 to the main storage device 4 to operate the main storage device 4. The main storage device 4 activates the acknowledge signal 7 when the operation for the access from the CPU 1 is completed, and notifies the CPU 1 and the cache 5 of the completion of the access. CP for main memory 4 and cache 5
U1 access includes read and write, and this distinction is notified to the main storage device 4 and the cache 5 by a read / write signal 9 output from the CPU 1.

FIG. 6 is an example of mapping of storage information in the main storage device 4 and the cache memory 5. As shown in the figure, the storage information of the main storage device 4 is mapped in units of blocks, and the blocks are stored in a plurality of columns 4a to 4h.
Is divided into On the other hand, the data memory of the cache 5
11 and the tag memory 10 are also divided into the same number of columns corresponding to the columns 4a to 4h.

One of the memory blocks existing in each column of the main storage device 4 is copied to the data memory 11 of the corresponding column of the cache 5. No two or more blocks in the same column of the main storage device 4 are simultaneously copied on the cache. The tag memory 10 has a data memory 11
Holds the address of the block being copied.

In the main storage device 4 and the cache 5 mapped as described above, one of the columns is selected by the lower data 2a of the address bus from the CPU 1. And the tag memory 10 of the selected cache 5
, The tag address is called by the comparator 12a, and the tag address is compared with the data of the upper 2b of the address bus from the CPU 1. When the data of the upper address 2b and the tag address hit, the data is output from the data memory 11 of the selected column to the CPU 1.

When the data of the upper address 2b and the tag address are not hit, the data is transferred from the main storage device 4 to the CPU 1.
At the same time, the data in the cache 5 is also updated to the data output from the main storage device 4 to the CPU.

For example, when the column 4a is selected by the lower 2a of the address bus, the tag address of the tag memory 10 is an address representing the block "0", and the data of the upper 2b of the address bus at this time is the block "0". If the address data is different from the address data, it is a mishit. Therefore, the data of the block (for example, “16”) represented by the address corresponding to the data of the upper 2b of the address bus is transferred from the main storage device 4 to the CPU.
And at the same time, the data memory of the cache 5
Block "16" is also transferred to 11, and the data is updated.

In a data processing device having the above configuration, the access speed to the main storage device is generally several times to ten and several times slower than the internal processing speed of the CPU. Therefore, if most of the memory reference is made to the cache, a processing speed equivalent to a machine cycle of the CPU can be obtained.

In the conventional cache, when the access from the CPU is mishit, the CPU refers to the necessary data from the main storage device as described above, and simultaneously transfers several tens of bytes of data including the necessary data to the cache. The data in the cache is replaced.

(Problems to be Solved by the Invention) The above-described conventional technology has the following problems.

As described above, in the conventional cache, data in the cache is always updated to another data in the main storage device whenever a CPU access mishits. However, the data held earlier in the cache may be more frequently used than the updated data. In such a case, by updating the data, the number of times that the required data exists in the cache (the hit rate) with respect to the number of accesses from the CPU decreases.

When the hit ratio is reduced, the data is often referred to from the main storage device. As a result, there is a problem that the processing speed cannot be significantly improved despite the provision of the cache. Therefore, it is desirable that frequently used memory blocks be copied from the main storage device to the cache.

The present invention has been made to solve the above problems.

(Means and Actions for Solving the Problems) In order to solve the above-described problems, the present invention provides a method for accessing data stored in a cache and a CPU access address when there is no data necessary for CPU access. Means for comparing the upper and lower relationship of the tag addresses, means for determining the relative distance between the two addresses, and means for outputting a data update request to the main storage device based on the result of the comparison and determination. There is.

According to the present invention having the above structure, when an access from the CPU does not hit, the access address is compared with the tag address of the data in the cache, and the data in the cache is compared with the data requested by the access. If it is determined that the usage frequency is higher than the usage frequency, the current storage data in the cache is not updated. Therefore, the problem that the hit rate is reduced by updating the data is solved, and the instruction processing speed in the data processing device can be improved as compared with the conventional cache.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

First, of the memory blocks stored in the main storage device,
A desirable development example will be described. FIG. 3 is a diagram showing the calling relationship of a certain series of programs, and FIG. 4 shows an example in which the programs are developed in one of the columns of the main storage device. Here, the pointed arrows in FIG. 3 indicate the number of calls.

In the calling relation of the program shown in FIG. 3, the program is composed of seven blocks A to G. As shown in the figure, the program of block A calls block B twice and block E once in the program. Further, block B calls block C three times and block D once, and block E calls block F twice and block G once.

Since such a calling relationship can be known at the time of compiling or linking a program, the blocks A to G are mapped from the lower address of the main storage device in descending order of the calling frequency.

The blocks A to G include a function group composed of blocks B to D based on the calling relationship, and blocks EG.
It is recognized that it is divided into a functional group composed of Therefore, blocks BD and blocks EG
Are arranged in close proximity to each other and in the order of higher calling frequency. FIG. 4 is a diagram showing a result of expanding the blocks in the main storage device in the order described above.

As described above, by arranging the blocks on the main storage device in accordance with the calling frequency of the blocks and the calling relationship, the one having the smaller address is used more frequently, The state that the probability of executing a series of functions in the memory access performed is high can be set on one column of the main storage device.

FIG. 1 is a block diagram of one embodiment of the present invention. 5, the same reference numerals as those in FIGS. 5 and 6 denote the same or equivalent parts.

In FIG. 1, the tag memory 10 and the data memory 11 collectively represent a plurality of divided columns.
The lower 2a of the address bus 2 is connected to the tag memory 10, and the columns of the tag memory 10 and the data memory 11 in the cache 5 are determined by the data of the lower 2a of the address bus 2. The arithmetic unit 12 has the upper 2b of the address bus 2
And the tag data output line 14 of the tag memory 10 are connected. The arithmetic unit 12 performs an operation such as a comparison between the data of the upper 2b of the address bus 2 and the tag address of the tag memory 10. One of the gates 13 for updating the tag memory 10 has an upper
2b is connected, and the other end is connected to the tag data output line 14 of the tag memory 10.

The arithmetic unit 12 compares the upper 2b data of the address bus 2 (hereinafter referred to as bus upper data 2b) with the tag address of the column whose entry is determined by the address bus lower data 2a. If the values are equal, a Hit signal 15 is output, and if the value of the bus upper data 2b is smaller than the tag address, a Low signal 16 is output. Also, bus higher data than tag address
When 2b is larger and the difference is larger than a predetermined value, a Far signal 17 is output.

The Hit signal 15, the Low signal 16, and the Far signal 17 are input to the controller 18, and the input / output operation to the cache 5 and the data update operation are performed in response to the output of each signal.

The controller 18 receives an access signal 6, a read / write signal 9, and an acknowledge signal 7 from the CPU 1, and outputs an operation signal 8 to the main storage device 4 from the controller 18. Further, a tag update signal 19 for updating tag data is output from the controller 18 to the tag memory 10 and the gate 13. When the update signal 19 is output, the gate 13 is opened, bus upper data is written in the tag memory 10 and stored as a new tag address.

The data input / output bus 20 of the data memory 11 is connected to the data bus 3 of the CPU 1 via the gate 21. Gate 21 is controlled by control signal 22 output from controller 18. Further, the data update signal 23 is output from the controller 18 to the data memory 11. When the data update signal 23 is output and the gate 21 is opened by the control signal 22, the data in the data memory 11 is replaced with new data via the data input / output bus.

Next, the operation of this embodiment having the above configuration will be described with reference to the drawings. FIG. 2 is a flowchart showing the operation of the controller 18.

In the figure, first, in step S1, it is determined whether or not the memory access signal 6 has been received from the CPU 1. If there is no access, the determination is negative and the process of step S1 is repeated. However, if there is access, the determination is positive and step S2 is performed.
Proceed to. In step S2, it is determined based on the read / write signal 9 whether or not the access is a write. If it is a write cycle, the determination in step S2 becomes affirmative, and the routine goes to step S3.

In step S3, the operation signal 8 is output and an operation request is issued to the main storage device 4. The main storage device 4 stores the data output from the CPU 1 in response to the operation request.

At step S4, it is determined whether or not the bus upper data output from the CPU 1 matches the tag address. If the tag address matches (hit), the process proceeds to step S5, where the control signal 22 is output.
At the same time, the gate 21 is set to the input side, and at the same time, the data update signal 23 is output, and the data output from the CPU 1 is taken into the data memory 11, that is, a so-called write-through operation is performed.
The new data is taken into the data memory 11 and the tag update signal 19 is output to open the gate 13 to update the tag address. If there is no hit, the determination in step S4 is negative and step S5 is skipped, and the data memory
The data of 11 is not updated, and an acknowledgment signal 7 indicating the end of the operation is output from the main storage device 4 to the CPU 1. Step when data is loaded into data memory 11
Return to S1.

In step S2, if the read / write signal 9 is a read signal, the determination in step S2 is negative and the process proceeds to step S6. In step S6, it is determined whether or not the bus upper data 2b has been hit. If hit, Hit signal 15 is detected and step S
The determination at 6 is affirmative, and the process proceeds to step S7 to output the data in the data memory 11 to the CPU 1. When the data is output to the CPU 1, an acknowledgment signal 7 for notifying the CPU 1 of the completion of the output is output (step S8), and the process returns to the step S1.

If bus upper data 2b is not hit, step
The determination in S6 is negative and the process proceeds to step S9. Step S9
In, it is determined whether or not the bus upper data 2b is smaller than the tag address, that is, whether or not the arithmetic unit 12 has output the Low signal 16. If the Low signal 16 has been output, the determination in step S9 becomes affirmative, and the process proceeds to step S10. When the Low signal 16 is output, the current cache 5
It is considered that an address in which data whose access frequency is higher than that of the address held therein, that is, the lower address in FIG. 4 is accessed, and an operation request signal is sent to the main storage device 4 in step S10. 8
Is output. In step S11, it is determined whether an acknowledgment signal has been output from the main storage device 4. The main storage device 4 responds to the operation request signal 8 and stores the data in the CPU 1.
When the acknowledge signal 7 is output, the determination in step S11 becomes affirmative, and the process proceeds to step S12.
In step S12, the same data as the data output from the main storage device 4 to the CPU 1 is taken into the data memory 11 in the cache, and stored in the column specified by the lower data 2a of the address bus 2 before the access. The data is updated.

When the loading of the data into the data memory 11 is completed, the acknowledge signal 7 is output to the CPU 1. When the fetching of new data into the data memory 11 is completed, the process returns to step S1.

If the low signal 16 is not output from the computing unit 12 in step S9, the determination in step S9 is negative and the process proceeds to step S13. In step S13, it is determined whether the Far signal 17 has been output from the arithmetic unit 12. F
If the ar signal 17 has been output, the determination in step S13 is affirmative, and the process proceeds to step S10. When the Far signal is output, access to a function group different from the data currently stored in the cache 5, for example, from the group (B, D, C) to the group (F, G, E), the processes of steps S10 to S12 are executed in the same manner as when it is determined that the Low signal 16 has been output in step S9 described above.

If the far signal 17 is not output, the determination in step S13 is negative, and the process proceeds to step S14. If the determination in step S13 is negative, the content stored in the cache 5 has a higher access frequency than the storage content of the address accessed from the CPU 1, that is, the address accessed from the CPU 1 is stored in the cache 5 now. It is determined from the stored tag address that it is higher in FIG. 4, and an operation request signal 8 is output to the main storage device 4 in step S14.

The main storage device 4 outputs data to the CPU 1 in response to the operation request signal 8, and outputs an acknowledge signal 7 to the CPU 1 when the output of the data is completed. When the operation request has been output to the main storage device 4, the process returns to step S1.

In this embodiment, as described above, the bus upper data 2b
And a tag address, and three types of signals, a Hit signal, a Low signal, and a Far signal, are obtained according to the upper / lower relationship between the addresses of the two data. Then, it is determined whether or not to update the data in the cache according to which of the signals is output. Therefore, the data considered to be frequently used is not updated, so that the hit rate can be improved.

It should be noted that the deviation between the bus upper data 2b and the tag address, which is a reference for outputting the Far signal 17, is the average of the address widths (L1 and L2 in FIG. 3) of each functional group of the blocks arranged close to each other. Set the value as a guide.

In this embodiment, an example has been described in which the arrangement of the blocks on the main storage device is determined at the time of compiling or linking the program. However, once the allocated program is executed several times, the data processing speed at that time is changed. The data processing speed can be further improved by rearranging the blocks again according to the characteristic information. Similarly, the deviation between the tag address and the bus upper data 2b set using the address width as a guide can be adjusted.

(Effects of the Invention) As is clear from the above description, according to the present invention, a cache with a high hit rate can be realized, so that the instruction processing speed in the data processing device is greatly improved as compared with the case where a conventional cache is used. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of a controller, FIG. 3 is a diagram showing an example of a program calling relationship, and FIG. FIG. 5 is a block diagram of an information processing system having a cache, and FIG. 6 is a diagram showing an example of data mapping. DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Address bus, 3 ... Data bus, 4 ... Main memory, 5 ... Cache memory, 6 ... Access signal,
7 acknowledgment signal, 8 operation request signal, 9 read / write signal, 10 tag memory, 11 data memory, 12
... Calculator, 15 Hit signal, 16 Low signal, 17 Far signal, 1
8… Controller

Claims (1)

(57) [Claims] 1. A program comprising a plurality of function groups each including a plurality of blocks,
A cache that maps each of the function groups with a predetermined address space and maps each of the blocks in the same function group from a lower address in descending order of the number of calls, and holds a copy of a part of the storage content of the main storage device In the memory, the difference between the tag address and the access address of the CPU is calculated, a Hit signal is output when the access address matches the tag address, and a Low signal is output when the access address is lower than the tag address. Means for outputting a Far signal when the signal is higher than the tag address by a predetermined difference or more, and is determined by the access address of the CPU when detecting the output of either the Low signal or the Far signal of the arithmetic means. Of the data memory belonging to the column of the cache memory Cache memory, characterized in that volume, and equipped with a controller for outputting a signal for requesting operation of updating the data of the access address in the main storage device.