JPH05120134A - Cache memory mounting system - Google Patents

Abstract

PURPOSE:To decrease a mutual interference by providing independently a cache memory used by a regular software and a cache memory used by a hardware control software, in an information processor for performing a part of hardware and firmware functions with the hardware control software. CONSTITUTION:The system is provided with a register 21a for showing a start address and a register 21b for showing an end address in a hardware area in a memory, and in the case an access to the memory is within a range determined by the registers 21a and 21b, a cache memory 22a is used, and in other case, a cache memory 22b is used. In such a way, an interference related to the cache memory of an access to a regular software area and an access to a hardware area is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory mounting method in an information processing apparatus for performing a part of hardware / firmware functions by hardware control software (hereinafter abbreviated as HCSW).

[0002]

2. Description of the Related Art Conventionally, in this type of information processing apparatus,
HCS of hardware / firmware function for the purpose of reducing control memory capacity and firmware design amount
W has been made.

The HCSW is coded by a software instruction group selected from all the instructions released to general software and an HCSW support instruction group dedicated to HCSW, and stored in a hardware area of the main memory.

As one of the operation modes of the central processing unit,
There are software mode and HCSW mode. In the software mode, the software manages the contents of the instruction counter, base register, general-purpose register, etc., and the CPU operates based on the instructions of the software.
In the HCSW mode, the contents of the instruction counter, base register, general-purpose register, etc. managed by the software are saved, and the CPU operates based on the instructions of the HCSW.

The HCSW is activated by hardware / firmware when necessary, and enters the HCSW mode.
After the processing is completed, the software mode is entered.

In this type of information processing apparatus, a cache memory is generally mounted for the purpose of speeding up main memory access, but until now, main memory access in the HCSW mode and main memory access in the software mode have been implemented. There was no particular distinction, so main memory accesses in both modes shared the same cache memory.

[0007]

In the above-mentioned conventional information processing apparatus, most of the main storage areas accessed in the HCSW mode are concentrated in the hardware area. On the other hand, in the software mode, the hardware area of the main memory is rarely accessed.

Therefore, the same cache memory is
In the conventional cache memory mounting method in which the SW mode and the software mode are shared, main memory accesses made in the cache memory in the respective modes interfere with each other, which causes a decrease in performance.

[0009]

According to the cache memory mounting method of the present invention, in an information processing apparatus for performing a part of hardware and firmware functions by hardware control software, access to a main memory is performed by hardware. It has means for distinguishing between an area and a software area, a cache memory used for accessing the hardware area of the main memory, and a cache memory used for accessing the software area of the main memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory view showing an embodiment of the present invention. In the figure, an information processing apparatus for implementing the present invention includes a main memory unit (MEM) 1, a central processing unit (CP).
U) 3, and system interface unit (SI
U) 2.

The central processing unit 3 includes a memory buffer control unit (MBU) 4 and a preceding control unit (PFU).
5, and an instruction execution control unit (EXU) 6.
Memory buffer control unit 4, advanced control unit 5,
The instruction execution control unit 6 is connected to each other.

The instruction execution control unit 6 has a working memory (W
S) 7 and CS control unit (CSU) 6a. CS
The control unit 6a includes a control memory (CS) 6b. The control memory 6b includes firmware (FW) 6c.

The memory buffer control unit 4 includes a high speed address translation buffer (TLB) 4b and a cache memory (CM) 4a.

FIG. 2 is an explanatory diagram showing the structure of the main memory.
The main memory is the hardware area 11 and the software area 10.
It is divided into a and 10b. The hardware area includes a HCSW instruction group 111, a work area 112 used by the HCSW instruction group, and hardware / firmware / HCS.
The control tables 113 used by W are stored.

The fetching of the HCSW instruction group is limited to the hardware area, and most of the main memory area accessed by the HCSW instruction group is concentrated in the hardware area. In addition, since the access to the hardware area is generally restricted in the software mode, the degree of isolation between the two areas is considerably high.

FIG. 3 is an explanatory diagram showing the structure of the memory buffer control unit. In the figure, the cache memory 2
2 is a portion 22a used to access the hardware area 11 of the main memory and the software area 10 of the main memory.
Portion 22b used to access a and 10b
Split into.

Now, assuming that the hardware area in the main memory takes a series of addresses, the memory buffer control unit 20 is provided with a register (UBR) 21b indicating the upper limit of the hardware area of the main memory and a register (lower) indicating the lower limit. LB
R) 21a is provided. The management unit 21 of the cache memory stores the address information regarding the access from the preceding control unit 5 and the contents of the registers 21a and 21b.
Input to the input comparator 21c. The access request from the preceding control unit 5 is transmitted to the registers 21a and 21b
If the access request is outside the range specified by the register, the cache memory 22a is referenced and updated by determining that the access is to the hardware area of the main memory. The cache memory 22b is referenced and updated by determining that the access is to the software area of the storage.

Therefore, regarding the access to the cache memory, the access to the hardware area and the software area is performed independently.

[0020]

As described above, according to the present invention, the cache memory is divided into a part used for accessing the hardware area of the main memory and a part used for accessing the software area of the main memory, thereby making the same. Compared with the conventional cache memory mounting method in which the cache memory of the cache memory is shared between the HCSW mode and the software mode, it is possible to reduce the interference of the main memory access performed in the mutual modes on the cache memory, and the performance due to this can be reduced. It has the effect of preventing deterioration.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an internal configuration of a main memory.

FIG. 3 is an explanatory diagram showing a configuration of a memory buffer control unit.

[Explanation of symbols]

1 main memory unit 2 system interface unit 3 central processing unit 4 memory buffer control unit 4a high-speed address conversion buffer 4b cache memory 5 preceding control unit 6 instruction execution control unit 6a CS control unit 6b control memory 6c firmware 7 working memory 10a, 10b main Software area of memory 11 Hardware area of main memory 21a Hardware area lower limit address register 21b Hardware area upper limit address register 21c 3 Input comparator 22a Hardware area access cache memory 22b Software area access cache memory

Claims (1)

[Claims] 1. In an information processing device for performing a part of hardware and firmware functions by hardware control software, a means for distinguishing whether access made to a main memory is a hardware area or a software area, and a main memory. A cache memory mounting method comprising: a cache memory used for accessing the hardware area of the main memory; and a cache memory used for accessing the software area of the main memory.