JPS6180438A - Cache memory - Google Patents

Abstract

PURPOSE:To attain the dynamic selection of an erasion system for the contents of a cache memory by providing an address register, cache RAM, the 1st comparator, a boundary register, the 2nd comparator, a counter selection means respectively. CONSTITUTION:Three effective displays V141, V244 and V345 are available, and a boundary register 70 and the 2nd comparator 71 are used to decide whether the address set at an address register 30 shows the 1st or 2nd main memory. Based on the result of said decision, an effective display is fed to decide the use of the V141, V244 or V345. A selector 49 serves as a switch circuit and selects the V141 with the 1st main memory. Either the V244 or V345 is used is decided by the value set at an FF60.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a cache memory of a data processing device, and particularly to a method for efficiently erasing its contents (prior art). A high-speed storage device that is placed between a high-speed processing device and has the effect of increasing the effective operating speed of the processing device by storing information that is frequently accessed by the processing device. be. It is now assumed that nine cache memories are provided for each processing device.

Here, when rewriting the contents of an address in the main memory by another processing device that shares the main memory, if the cache memory contains the information at the address before rewriting, then need to erase it. In the first erasing method, each time a processing device rewrites the contents of the main memory, the corresponding address is notified to other processing devices, and the contents of the block containing the corresponding address in the internal cache memory of the other device are also simultaneously erased. It is something to be erased.

The second erasing method does not erase the contents of the cache memory each time a rewrite is performed, but erases the entire contents of the intermediate memory at a timing required by the logic of the program.

Usually, the above-mentioned method 1F, 2 is adopted. Although the second method requires less hardware, there is a problem in that the hit rate of the cache decreases and the performance of the processing device is greatly degraded due to this. Therefore, the gt method is often adopted. However, in cases such as multiprocessor systems that consist of different types of processing units and main memory, the first method is not possible, and the second method has a much lower performance penalty. There is a weir.

For example, FIG. 2 shows a lot of two central processing units.

102 and two main storage devices 103 and 104 are connected to one system control unit (105). In FIG. 1, a second central processing unit 1
02 and the second main storage device 104 are devices having extremely large data transfer capabilities compared to the first central processing unit 101 and the first main storage device 103, respectively.
Usually the first central processing! The IE device 101 has many opportunities to access the first main storage device 103, and the second central processing unit 102 has many opportunities to access the second main storage device 104. However, sometimes there is an opportunity to access the main memory on the opposite side, and in such cases, the cache memory of the first central processing unit 101 is transferred to the second central processing unit 10.
2, I forgot to write to the second main memory device 104 at high speed and could not erase the address corresponding to the address of the main memory device. Therefore, at the timing of 'J? It becomes necessary to erase all the contents of the cache memory of the central processing unit 101 in 'a'. However, the first central processing 1i10
Since most of the contents of the L cache memory are those of the first main storage device 103, wasteful erasure will be performed and performance will be degraded.

FIG. 3 is a block diagram illustrating a part of FIG. 2 in detail. In FIG. 3, a system control unit 105 is a device that organizes access from the first and second central processing units 101 and 102 to the first and second main storage devices 103 and 104. Interface signal lines 2 to 5 for main memory access generally carry main memory access commands (0), main memory addresses (A), and write data (W).
D) and read data (RD). Reference numerals 3 and 5 are interface signal lines each having a high transfer capacity and a large data width. Therefore,
The cycle time required to transfer command addresses and data is short.

From the second central processing unit 102 to the first main storage device 103
When a write access is made to the first main memory 1
The address information included in the signal line 11 to 03 is also sent to the first central processing unit 101 via the signal line 12, and the first central processing unit lo1 erases the contents of the cache memory (the corresponding address). It will be done. Erasing the contents of the cache memory at the address in response to writing by another device can be performed using a very general technique, so a detailed explanation will be omitted.

(Problems to be Solved by the Invention) As explained above, the cache memory content erasing method according to the prior art has the problem that the access performance deteriorates due to hardware constraints.

An object of the present invention is to notify the cache memory of the first central processing unit of the corresponding address in the case of writing to the first main memory, erase it each time the write is made, and write to the second main memory. In this case, the above drawback is eliminated by erasing all the information in the second main storage device inside the cache memory at a different timing instead of erasing it each time, and the hit rate decreases less when erasing the contents. The purpose of the present invention is to provide a cache memory configured as follows.

(Means for solving the problem) A cache memory according to the present invention includes an address register,
It is configured to include a cache RAM, a first comparator, a boundary register, a second comparator, a counter, and selection means.

The address register is for storing a main memory address.

The cache R and AM have some fields of the main memory address as an address field and a valid display field, and other fields as data fields.

The first comparator compares the address of the cache RAM with an address inside the address register, and detects a hit in the cache RAM when the two addresses match.

The boundary register stores the boundary address between the first and second main memory devices, assuming that the main memory addresses are consecutively given to two different first and second main memory devices. It is for the purpose of

The second comparator compares the address forming part of the address register with the contents of the boundary register to distinguish between the first and second main memories.

The counter is for providing an address counter to keep resetting the valid indication of the unused A of the first and second main memories.

The selection means displays the usage states of the two main storage devices determined by combining the cache RAM, the counter, the address counter, and the second comparison circuit according to the cache R and AM valid display fields; This is for selectively giving an instruction to write/erase cache contents to an external peripheral device so that the contents can be erased from the first main memory each time it is written.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of a cache memory according to the present invention.

In Figure 1 h, 30 is an address register, 31°32
are internal fields of the address register 30, respectively,
40 is a cache RAM, 41 is a valid display field, 42 is an address field, 43 is a data field, 44.45 is a valid display field, 46 to 49 are selectors, 50 is a first comparison circuit, 51 is an AND circuit, 60
7 is a lip-flop, 61 is a counter, 70 is a boundary register for holding the boundary address between the first and second main memory devices, and 71 is a second comparison circuit.

In FIG. 1, some fields of the main memory addresses set in the address register 30 are RA for middle storage.
This will be the address of M40. At this time, if the cache memory is hit b, the target data is read from the data field 43 of the cache RAM 4o. - Internal field of cache RAM M2O 41゜4
2 constitutes a directory, and the contents of the address field 42 and the valid display field 41 in some of the address registers 30 are 11#.

In other words, it is considered to be a hit when it is "valid".

In this embodiment, the effective display is Vt (41), Vl (4
4).

The boundary register 70 and the second It is judged by the comparator 71 of
). The selector 49 is a switching circuit for the above switching, and is a switching circuit for the above switching.
When , Vs (41) is selected. vl(
Which of 44) and Vl(45) to use is determined by
It is determined by the value set in the flip-flop 60.

For example, the value set in the flip-flop 60 is MO
”, Vl (44) is selected by the selector 48. At this time, the value set in the technical address register 30 as the address of Vz (44) is selected by the selector 46, and the address of Vs (45) is The value set in the counter 61 is selected and given by the selector 47.The counter 61 is used to reset the unused valid display bit during the operation of the cache memory. .

Erasure of all contents of the cache memory related to the second main memory device 104 is instructed by a no-aware instruction at a timing required by the logic of the program. However, when the above display is sent out, the flip 70 knob 60 is inverted and becomes 11#.

As a result, Vl (45) is used to indicate whether the second main storage device 104 is valid. At this time, the contents of v3 are already @
Since it is reset to 0#, all information related to the second main storage device 104 stored in the cache memory at this stage has been erased.

Since the above address has been switched to the counter 61, the contents of Vl (44) are thereafter reset at a rate of one word per machine cycle as the counter is updated. After the above reset is completed, when erasing all information in the second main storage device 104 is instructed again, vl is used by inverting the flip-flop 60, and the erasing of all the contents is performed. It has been done.

The surrounding address information sent along with the writing of data to the first main storage device 103 (therefore, each time, Vt (41)
The contents of will be deleted. Details of this method are known. By applying pressure as described above, the first and second main storage devices 103
, 104, the erasure of the contents of the cache memory is achieved by the respective optimal method. In order to display the validity of the second main memory bag f104, vl
Assuming that only (44) is defined, Ao cannot refer to the cache memory while Vl is being deleted. If the display is limited to vl only, the erasing operation is performed using address field 4 inside the cache RAM 40.
It is necessary to read part of 2 and erase it while checking that it is the address of the second main memory device 104.

In any case, the apparent time required to erase the contents of the cache memory is much longer than in this embodiment. However, in this case, the contents of the cache memory are
It is possible to avoid deterioration in the performance of the processing device due to erasing all information including the information in the main storage device 103.

(Effects of the Invention) As explained above, the present invention improves the performance of a system formed by combining different types of devices by dynamically selecting the erasing method for cache memory contents. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of a cache memory according to the present invention. FIG. 2 is a block diagram showing a general connection relationship between central processing electronics and storage devices in a data processing system. FIG. 3 is a block diagram showing a part of FIG. 2 in detail. 30... Address register 4o... RAM M4
6 to 49... Selector 50.71... Comparison circuit 51... AND circuit 60... Flip-flop 61... Counter 70... Register 31.3
2.41-45...Fields 101, 102...
・Central processing unit 103, 104...Main storage device 105...System control unit 2-5, 11.12...Signal line Patent applicant NEC Corporation Representative Patent attorney Hisashi Inoro/I' l
mouth

Claims (1)

[Claims] an address register for storing a main memory address; a cache RAM having some fields of the main memory address as an address field and a valid display field and other fields as data fields; a first comparator for comparing an address with an address forming a part of the inside of the address register and detecting a hit in the cache RAM based on a match between the two addresses;
a boundary register for storing a boundary address between the first and second main storage devices as consecutively given to different first and second main storage devices; and a boundary register for storing a boundary address between the first and second main storage devices; a second comparator for distinguishing between the first and second main memories by comparing an address forming the part of the register with the contents of the boundary register; and a second comparator for distinguishing between the first and second main memories; a counter for providing an address count so as to keep resetting the validity indication of the unused device; and an R for the cache.
AM, the counter, the address register, and the second comparison circuit determine the usage states of the two main storage devices in the cache R.
a selection means for displaying in accordance with a valid display field of AM and selectively giving instructions for writing and erasing cache contents to an external device so that the contents can be erased from the first main storage device each time it is written; A cache memory comprising: