JPS6124737B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an input/output control device. A conventional input/output control device is equipped only with a control storage circuit for storing control information having a plurality of transfer control blocks. As a result, when the input/output control program of the data processing device writes memory addresses, transfer control information, etc. to a transfer control block, or reads status information from a transfer control block, it must specify the number of the corresponding control block. . Therefore, the input/output control program must update and manage the control block number every time it executes a write or read command to a control block, and furthermore, it must update and manage the control block number to prevent the number of writes or reads from exceeding. There is a drawback that the comparison between the number of reads and the number of reads must also be performed by the input/output control program. SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output control device that eliminates the need to manage control blocks of an input/output control program for a data processing device. The device of the present invention includes means for storing transfer control information for controlling data transfer between a main storage device and an input/output device in a plurality of storage locations, and an operation for writing a write address indicating the storage location of the storage means. write address generating means that generates a write address by changing a fixed number each time; a write means that writes the transfer control information from the data processing device to a storage location designated by the write address; and a storage location of the storage means. read address generating means that generates a read address by changing a read address indicated by a fixed number for each read operation; a reading means for reading control information; a data transfer means for transferring data between an input/output device and the main storage device under the control of the transfer control information read by the reading means; Monitoring information is sent to the data processing device to the effect that when the value obtained by adding the number of writes and subtracting the number of reads by the reading means is 0, an excess of reading is detected, and when the value exceeds the total number of storage positions of the storage means, an excess of writing is detected. and monitoring means for transmitting the data. The present invention will be explained in detail using figures. FIG. 1 is a diagram showing an input/output control device according to an embodiment of the present invention. When a data processing device 2 executes a buffer control block information output command, the input/output control device 1 outputs memory addresses, ranges, etc. control information is set in the buffer control circuit 20,
When the transfer start command is executed, the memory location of the main storage device 3 specified by the buffer control circuit 20 and the input/output transfer of data are executed by the transfer control circuit 2.
1, data input/output is performed with the input/output device 4 via the input/output device control circuit 22,
When a predetermined transfer with the main storage device 3 is completed, an interrupt signal is given to the data processing device 2 via the data processing device interface circuit 23, and when a transfer status input command is executed in the data processing device 2,
This is a device that provides transfer status from the buffer control circuit 20 to the data processing device 2.

[Table] The table shows the buffer control block in this embodiment. There are four control blocks: control block 0, control block 1, control block 2, and control block 3. These control blocks are used cyclically with reference numbers 0, 1, 2, 3, 0, etc. to control data transfer. will be held. Each control block has the same format and consists of memory address, range, control and status fields. The address field stores the memory address location on the main memory for the next transfer, and is incremented by 1 every time one word is transferred to/from the main memory. The range field stores the number of words left in the main memory 3 for input/output transfer, and is decremented by 1 every time one word is transferred, and when the content becomes 0, the transfer ends. . The control field contains control information such as a valid flag and whether to interrupt the data processing device at the end of the transfer. The status field is used to store information such as whether the transfer was completed normally or abnormally. FIG. 2 is a diagram showing the buffer control circuit 20 in the input/output control device shown in FIG. 1. In FIG. 2, reference number 11 is a 32-byte memory that stores the control blocks shown in the table; reference number 12,1
3, 14, and 15 are 2-bit counters; 16 is a 2-bit selector for various signals 105, 106, and 107; reference number 17 is a 3-bit selector for lower addresses 110 and 111; reference number 18 is for input data 114 and 8 bits to select 115, reference number 19 is counter 15
101 is a 2-bit register storing outputs 122 and 123 of counters 12, 13,
14 and 15 and a clear signal for register 19, reference number 102 is a count up signal for counters 12 and 15, reference number 103 is a signal for counting up counter 13 and counting down counter 15, reference number 104 is a count up signal for counter 14. , reference number 105,1
06 and 107 are counters 12 and 13, respectively.
and 14 output 2 bits, reference number 108 is the upper 2 bits of the memory address of memory 11, reference number 112 is the lower 3 bits of the memory address of memory 11, reference number 116 is the 8 bits of input data to memory 11, reference number 120 is 8-bit output data of the memory 11, reference number 119 is a write signal of the memory 11, reference numbers 109 and 113 are selection signals of the corresponding selectors, reference numbers 110, 11
4 and 117 are the lower 3 bits of the memory 11 address, 8 bits of input data and memory write signals from the data processing device interface circuit 23, reference numbers 111, 115 and 118, respectively.
are the lower 3 bits of the address of the memory 11 from the transfer control circuit 21, the input data 8 bits 1 and the memory write signal, respectively, and the reference number 121 is the latch clock signal of the register 19 generated by the count signal 102 or 103, reference number 1
22 is a carry output signal of the counter 15, reference number 123 is a borrow output signal of the counter 123, reference number 124 is an output of the register 19 and is a control block overflow signal, and reference number 125 is an output of the register 19 and is a control block underflow signal. . When initializing the input/output control device, the counter 12,
After the contents of registers 13, 14 and 15 and register 19 are initialized, selectors 16, 17 and 18 are selected as inputs 107, 111 and 115, and input signals 115 and 111 are set to "0".
is given and the memory write signal 1 is output from the signal line 118.
19 is output and memory location 0 is “0”
is set to Below, memory address signals 112 and 108 are set to +1 by signals 111 and 104.
After the write signal 119 is output while being added and all memory locations in the memory 11 are set to "0", the counter 14 is set to off. The setting of a control block from the data processing device to this control device is performed by an instruction sequence of an address output command, a range output command, and a control output command, and the operation of inputting the state information of the control block to the data processing device is performed by a state information input command. Or by the following information input command. When the address output instruction is executed, selectors 16, 17 and 18 output inputs 105, 110 and 114, respectively.
After the side is selected, information on the lower byte of the memory address from the data processing device 2 is given as logic “0” data 114 as the lower address 110, and a write signal 119 is generated by the write designation signal 117 from the data processing device interface circuit. The information is written to byte 0 of control block 0, and then the lower address 110 is set to logic “1”.
When the information of the middle byte of the memory address is given as data 114 and the write signal 119 is given, the information is written to byte 1, and similarly the signal 110 from the data processing interface circuit 23,
114 and 117 are controlled and the upper byte of the memory address is written in byte 2. When the range output command is executed, the signal lines 110, 1 from the selectors 16, 17 and 18 and the data processing interface circuit 23 are
14 and 117 are controlled to write lower range and upper range information to bytes 3 and 4 of control block 0. When the control output command is executed, control information is written to byte 5 of control block 0 and logic "0" is written to bytes 6 and 7 by the same circuit operation as the address output command, and then the count up signal 102 is written. The states of the generated counter output signals 122 and 123 are stored in the register 19, and the counters 12 and 15 are incremented by +1, and the next control block to be set becomes control block 1. Hereinafter, each time a control block set command sequence is executed from the data processing device, a write operation to the memory 11 and a +1 addition operation to the counters 12 and 15 are performed, and the control block set is cyclically controlled. If the overflow signal 124 is set when the address output command is executed, a response is sent to the data processing device 2 to deny the command execution, thereby preventing overwriting of the control block. When the next status display signal input command is executed, the selectors 16 and 17 select the output 106 of the counter 13 and the lower address 110 from the data processing device interface circuit 23, and then the lower address 110 is set to “6”. ” is set and the status 2 of control block 0 is read out as memory output information 120 and sent to the data processing device interface circuit 23 via the transfer control circuit 21.
Then, "7" is set in the lower address 110 and the contents of status 1 are read out as information 120.
After the count signal 103 is generated and the states of the count result signals 122 and 123 are stored in the register 19, the counter 15 is incremented by -1, the counter 13 is incremented by +1, and the status is input. The control block is designated as control block 1. Thereafter, each time the next state information input command is executed, the state information is read and the counters 13 and 15 are updated, and the state information read operation from the control block is cyclically controlled. If the underflow signal 125 is set when the next status information input command is executed, a response is sent to the data processing device to deny execution of the command, thereby preventing excessive state information reading. Execution of the status information input command is similar to the next status information input command, but the count signal 103 is not generated. Next, the operation when the transfer control circuit uses control blocks will be explained. Selector 16, 17
After the information on the inputs 107, 111 and 115 is selected in steps 18 and 18, "5" is set in the lower address 111 and the control information is transferred to the memory 1.
1 as read information 120, and the following operations are executed only when the valid flag is set. “0” is sequentially added to the lower address 111,
“1”, “2”, “3” and “4” are set and the memory address lower, middle, upper, range lower and upper bytes are read out as read information 120, and the memory address information and upper bytes are read out to the transfer control circuit 21. Range information is issued. Transfer control circuit 21
When the transfer of one word to the main memory device 3 is completed, the previously read memory address information is incremented by +1, the range information is incremented by -1, the lower memory address information is given to the input line 115, and the input line 111 receives a logic 0. “0”
After this is applied, a memory write signal 119 is generated by a write designation signal 118 from the transfer control circuit 21, and the contents of byte 0 of control block 0 are updated. Next, the data information applied to input 115 and the value set to input signal 111 are changed to memory address middle, upper, range lower, upper, and 1, 2, 3, 4, and write signal 119 is generated. 2, 3 and 4 are updated.
The above operation is repeated until the range information becomes logic "0". When the range information becomes logic "0", byte 6 of control block 0 is cleared by the same operation as above.
and 7 after the state information is written to the signal 104
is generated, the counter 14 is incremented by +1, and the next control block to be used is designated as control block 1. Thereafter, each time the range information becomes "0", the state information is written to the memory 11 and the counter 14 is added +1, and the control block is set to 0,
1, 2, 3 and 0... are used cyclically. If the use management of the four control blocks is executed by the input/output control device as in this embodiment, it becomes unnecessary to manage the control blocks for input/output control by the data processing device program, reducing the number of steps in the input/output control program and reducing the execution time. is shortened. The present invention includes an input/output control device that performs control block write, use, and status read operations cyclically in the same order, and monitors whether the number of writes or reads of a control block is exceeded. This has the effect of reducing the number of input/output control program steps and execution time of the data processing device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an input/output control device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a buffer control circuit in the input/output control device of FIG. 1. 1 and 2, 1... input/output control device, 2... data processing device, 3... main storage device, 4... input/output device, 11... memory, 12,
13, 14, 15...Counter, 16, 17, 1
8... Selector, 19... Register, 20... Buffer control circuit, 21... Transfer control circuit, 22...
...I/O device control circuit, 23...Data processing device interface circuit.

Claims (1)

[Scope of Claims] 1. Buffer address information of a buffer area on the main storage device, including buffer arrangement information and control information, for controlling data transfer between the buffer area on the main storage device and an input/output device. at least 1
storage means for storing one transfer control block in a plurality of storage locations; and the transfer generated by changing a first address indicating the storage location of the storage means by a fixed number for each write operation and supplied from a data processing device. writing means for writing a control block to a storage location specified by the first address; and a second address indicating the storage location of the storage means that is generated by changing a fixed number of addresses from the data processing device for each read operation. a first readout means for reading control information in the transfer control block to the data processing device from a storage location of the storage means specified by the second address in response to a readout command; a second reading means for reading buffer address information and buffer arrangement information in the transfer control block from a storage location of the storage means; Transfer control means for controlling data transfer between the main storage device and the input/output device based on the contents of the transfer control block sent to the second reading means and read from the storage means; and the writing means. The value obtained by adding the number of writes by and subtracting the number of reads by the first reading means is 0.
An input/output control device comprising: monitoring means for transmitting monitoring information to the data processing device indicating that an excess write occurs when the excess read exceeds the total number of storage positions of the storage means.