JPS5814260A - Data transfer system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an OPU and multiple media sharing the same data path.
The present invention relates to a data transfer method intended to increase the transfer speed by transferring data between memories using an OPU-mediated method and writing data by adding a small amount of hardware (circuit).

On a general-purpose computer, after turning on the power, the first thing to do is
The so-called IPL (abbreviation for ry) is made to take a gun
alProgram Load) is required to be performed efficiently.

Such IPL target programs include, for example, paper tape, magnetic tape, and ROM (Read Only Memo).
FORTRAN% stored in memory media such as
There are programs that do not require a series of changes, such as the BA8IO interpreter program. Conventionally, in order to transfer a program from these media to the RAM, the CP
U reads data and stores it in RAM or DM
It was transferred in person.

Figure 1 is an example of data transfer from ROM to 8AM. In other words, the figure shows the OPU-mediated method - a group of data is RA'd.
When transferring data to M, a ROM is provided in parallel with the RAM.
OM and RAM both address 100OH to 2FF'F
The memory bank switching circuit 3 enables the ROM and RAM alternately, and the OPU transfers data while repeating the operations of reading data from the ROM, switching over punctures, and storing data in the RAM. is done.

READ and WRITE in FIG. 1 indicate that command signals are sent for the CPU to read data from the ROM side (READ) and for the OPU to write and store data in the RAM (WRITE). However, such OPU-mediated data transfer is slow because the R, EAD, and WRITE operations are alternately repeated.

To improve this, DMA (Dlrect KiemoryA) is used to directly transfer data from ROM to RAM.
Although this may be done using the DMA method, the hardware is complicated. In addition, the ROM can be used as an I/O controller for input/output control.
Even if it is provided within 10 areas, it is unavoidable that the hardware becomes complicated, such as requiring a ROM access counter.

The object of the invention is to eliminate the above-mentioned disadvantages. To achieve the object, the present invention provides a computer that transfers data between an OPU and a memory via a data bus.
Main memo where all or part of the address matches the RAM address and the data bus also matches! lRA
A read command or a read command from OPU When executing the operation according to the command, the output data from the ROM can be loaded into the RAM area corresponding to the address.

Below, referring to the circuit shown in FIG. 2 which shows one embodiment of the present invention, the main constituent means thereof will be explained. That is, Figure 2 is sugar 1
As is clear from the comparison with the figure, the data transfer from ROM to RAM requires only a small number of additional nodes, requires fewer instructions from the CPU, and improves the transfer speed and privacy. When this is completed, the ROM side data bus 2' is disconnected.

In FIG. 2, the main memory RAM has a standard memory capacity of, for example, 64 kilobytes, and
The 1000H to 2FFPHJC of 8 Kbytes coexists with the ROM. During the IPL operation within this coexisting address, the RAM READ and WRITE signals are supplied via an AND-OR circuit shown at the bottom of the figure. The input of the AND-OR circuit consists of the above-mentioned signal and a switching signal, and the logic of the switching signal allows the REA to be output from the CPU.
READ/WRI in D/WRITE and I'LAM
The TEs are made to match or swap.

The flip 70 knob F/F is set to Q-1 during IPL operation, and is set to Q-0 at other times. The ROM and RAM address detection circuit has an example of 1000 to 2FFF operation.
It discriminates the address from the encoder, person, person, and I, outputs 1 to the output side C in the address matching area, and outputs C-0 and T in other addresses, for example, it is composed of NOR and EXOR circuits.

The data transfer means of the present invention is first set to Q-1 of F/F, and READ (!:WRITB) is input to ordinary person M.
Replace the signals and enable the ROM, then remove 0) 4C1000~2PPP7 Vvx OP UjCRE
Make AD. This address is 0 since it is the matching area.
-1 is output, and the B side is valid in the AND-OR circuit, that is, a write (WRI'rl) operation is performed on the 9 AM regardless of whether it is an OPU read (RFiAD). At this time, the accessed address data from R□M is output to path 2 and also supplied to RAM ◎ That is, from ROM to RAM
Data will be transferred to. In the conventional OPU intervention method, after data is RBADed from ROM, RAMKWR
A two-stage I'l'E operation is required, but according to the present invention, data transfer to RAM is performed only with a READ operation, so the data transfer speed is approximately double the Q output of the F/F (or Q output) to E to ROM
By giving it as a NABLE signal, the ROM becomes valid only during PL operation, and when other than IPL operation, the F/F is cleared and the ROM becomes invalid.The same is true even if the ROM is separated in the memory space.There is no influence of R/9M. Not at all.

In the description of the embodiment, amAD and WI'LITF
Although the circuit is shown separated from t, and the logic circuit is also shown as an AND-OR circuit, this circuit can take various forms. Some have only one READ and WRITE signal, but in this case, if READ is at H level, if you forcibly lower the L level to ζ, the same inter-memory data transfer as described above will be executed. Become.

As described above, according to the data transfer method of the present invention, simple hardware (
The transfer speed can be nearly doubled by changing the circuit) configuration, and if this is used for operating codes such as 8-bit-R icon engineering PL, the effect will be great.

[Brief explanation of the drawing]

FIG. 1 shows an example of a conventional data transfer circuit, and FIG. 2 shows a data transfer circuit diagram according to an embodiment of the present invention.

Claims (1)

[Claims] OPU via the data bus! : A computer that transfers data between memories is equipped with a main memory RAM in which all or part of the ROM address matches the RAM address and the data bus also matches, and detects an address match area between the ROM and RAM. and a means for forcibly reversing read and write commands from the CPU to the RAM and setting the valid/invalid state. A data transfer method characterized by being able to write to a RAM area.