JPS6027401B2 - sequence controller - Google Patents

Description

Detailed Description of the Invention The present invention provides a data memory between an arithmetic processing section and an input/output unit, and exchanges on/off information from the input/output elements and on/off signals from the arithmetic processing section via this data memory. This is related to the sequence controller that was
The purpose of this is to speed up data exchange by making it possible to exchange on/off data independently of the program execution and execution by the arithmetic processing unit, and to connect the input unit and output unit. The purpose is to increase flexibility by allowing the address and the ratio of input units and output units to be changed freely.

In recent years, with the increase in the size of production machines, the so-called remote 10 method has been adopted, in which input/output units connected to input elements such as limit switches and output elements such as relays are distributed at locations away from the processing section. Sequence controllers have come to be used to control production machinery, etc.

In this type of sequence controller, if signals are exchanged directly between the input/output unit and the arithmetic processing section, the arithmetic processing cannot be performed at high speed due to the signal transmission delay. A data memory is provided on the side of the arithmetic processing unit to store on/off information from the input/output unit and an on/off signal sent from the arithmetic processing unit to the input/output unit, and the on/off information and the on/off signal are exchanged via this data memory. That's what I do. In other words, a data exchange device is provided between the data memory and the input/output unit so that on/off information and on/off signals are periodically exchanged, and the arithmetic processing section of the sequence controller uses the on/off information stored in the data memory. In order to test information as information from input/output elements and to energize or deenergize output elements specified by the program based on the test results, on/off information is stored in the storage area corresponding to the specified output element in the data memory. It is designed to write signals. By the way, rewritable semiconductor memory, which is generally used as data memory, cannot write and issue data at the same time. It must be ensured that reading and writing do not occur at the same time.

For this reason, conventionally, one reference clock is alternately applied to the arithmetic processing section and the data exchange device. As a result, each time the arithmetic processing unit executes several sequence programs, the on/off signal or on/off information of the input/output element is transmitted bit by bit between the input/output unit and the data memory, and the sequence program is executed - times. Then, all of the on-off signals that energize or de-energize the output elements are transferred to the input/output unit, and all of the on-off information from the input elements is written to the data memory. This prevents the data memory from being accessed simultaneously by the arithmetic processing section and the data exchange device, but in this case, the arithmetic processing section must be operated intermittently in synchronization with the reference clock. Therefore, the arithmetic processing unit must execute the sequence program one by one each time the reference clock is applied, and must stop the arithmetic processing operation each time the execution of the sequence program is completed.

Additionally, if the next reference pulse is given before the sequence program has finished executing, the operation will become abnormal, so an interlock circuit is required between the arithmetic processing unit and the circuit that generates the reference pulse. . For this reason, remote 1
The arithmetic processing section used in a general sequence controller other than the 0 method cannot be used as is, and a new arithmetic processing section dedicated to the remote 10 method must be designed and manufactured. In addition, in conventional sequence controllers, on/off information is transferred from the input unit to the data memory for the address where the input unit is connected, and on/off information is transferred from the data memory to the output unit for the address where the output unit is connected. Therefore, the address where the input unit is installed is completely distinguished from the address where the output unit is installed, and the address to which each unit is connected is used to determine whether each unit is an input unit or an output unit. I was trying to do that.

For this reason, the address at which the input unit is installed and the address at which the output unit is installed are fixed, and there is a problem in that the address at which the input unit and output unit can be connected and the mixing ratio thereof cannot be changed. The present invention has been made in view of this point, and includes two sets of input/output bus lines connected to the arithmetic processing unit and storage areas corresponding to the respective addresses of input/output elements connected to the input/output unit. a data memory, a timing signal generating means for outputting a signal at a time interval longer than at least the execution time of the sequence program by the arithmetic processing unit, and one data memory for switching the gate according to the signal from the timing signal generating means. During the period when the other data memory is connected to the input/output bus line, the other data memory is connected to the input/output unit, and during the period when the other data memory is connected to the input/output bus line, the one data memory is input/output. A terminal switching means is provided to connect the data memory to the unit, and each time the data memory is switched, on/off signals corresponding to all input/output elements are sent from the data memory to the input/output unit. The present invention is characterized by being provided with a data exchange means for reading on/off information of input/output elements from the input/output unit and writing it into the data memory.

Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, 11 and 12 are an input unit and an output unit, respectively.
are connected to the connection terminals 13 arranged at a remote position with respect to the sequence controller main body 201 at an arbitrary ratio and at an arbitrary position. This connection terminal 13 is connected to two sequence controller bodies via three bus lines ADB, mB, and ODB and a signal line 14. Note that the bus line ADB indicates an address bus, and the bus lines mB,
ODB indicates an input data bus and an output data bus, respectively. The input unit 11 converts the open/close states of input elements such as pushbutton switches 10 and 20, limit switch 10, and LS 20 connected to the input terminal 11a into TTL level on/off information. Eight input elements are connected to one input unit 11.

When one of the input units 11 is selected by the address data output to the address bus ADB, the open/close states of the eight input elements connected to the selected input unit 11 are input as 8-bit on/off information. It is designed to be output to the data bus IDB. on the other hand,
The output unit 12 energizes or deenergizes output elements such as relays and solenoids connected to the output terminal 12a based on on/off signals output to the output data bus ODB. In this embodiment, eight output elements are connected to the output terminal 12a. They are simultaneously activated or deactivated by an 8-bit on/off signal.

Inside the output unit 12, eight flip-flops are provided corresponding to the output elements connected to the output terminal I2a, and the on/off signal of the output data bus ODB is controlled by the latch signal output to the signal line 14. The output element is loaded into eight flip-flops at the same time, and the output element is activated or deactivated by setting or resetting the flip-flops. Also, this output unit 1
2, when selected by the address data output to the address bus ADB, the set and reset states of eight flip-flops are output to the input data bus mB as information indicating the on/off states of the output elements. . Next, we will explain the two main parts of the sequence controller.

This sequence controller main body 20 can be roughly divided into:
An arithmetic processing unit 21, two sets of data memories 22 and 23, a data exchange circuit 24, an address decoder 25, gates GI to GI2 for switching between the data memories 22 and 23, and a control circuit for opening and closing the gates GI to GI2. It is made up of. Arithmetic processing unit 21 is remote 10
This system uses a sequence controller that is common to general sequence controllers, rather than a dedicated sequence controller.

This arithmetic processing section 21 is composed of an arithmetic processing section 30, a program memory 31, and a program counter 32.
A predetermined sequence program is stored in the program memory 31 by a program loader (not shown).
The arithmetic processing unit 30 sequentially increments a program counter 32 in synchronization with an internal clock, and sequentially reads and executes the sequence programs stored in the program memory 31 starting from address zero.

In addition, since this arithmetic processing unit 3 is designed to input and output data in units of 8 bits, the arithmetic processing unit 30 uses the upper bits of the input/output address data programmed as a sequence program, such as the address If the data is 8 bits, the upper 5 bits of data are output to the address output bus AOB, and addressing is performed in units of input/output units. If the extracted Sequesos program is a test instruction, the 8-bit on/off information output to the data input bus DIB is extracted and the lower 3 bits of the address data are used to
The on/off information specified by the program is selected from the on/off information of the bit, and a test is performed using the selected on/off information. On the other hand, if the read sequence program is an output instruction, the data input bus DI
Inputs the 8-bit on/off information output to B,
From this read 8-bit data, the bit specified by the lower 3 bits of the address data is rewritten based on the test result, and the rewritten 8-bit on/off signal is output to the data output bus DOB. There is. Note that the arithmetic processing unit 30 outputs a latching strobe signal DOS in synchronization with the sending of the on/off signal. Therefore, when performing normal sequence control other than the remote 10 method using the above-mentioned arithmetic processing section 21, the data buses DIB, DOB, and AOB of the arithmetic processing section 21 are connected to the input/output units 1, 1, and 1.
The strobe signal DOS outputted from the arithmetic processing unit 30 may be outputted to the signal line 14.

Two sets of data memories 22 and 23 store the on/off signals of the output elements sent from the arithmetic processing section 21 and the input/output unit 1.
By providing the data memories 22 and 23, the distance between the sequence controller main body 20 and the input/output units 1 and 12 is increased, and signal transmission is facilitated. Even if it takes a long time, the arithmetic processing device 30 can perform the arithmetic processing at the highest speed.

The data memories 22 and 23 are both composed of rewritable semiconductor memories, and the input/output units 11 and 1 are connected to the sequence controller main body 2.
A storage capacity corresponding to the maximum number of 2 is used. In this embodiment, the address data specifying the input/output units 11, 12 is composed of 5 bits, and the input/output units 11, 1
Since eight input/output elements are connected to each of the data memories 22 and 23, a memory of 32 words and 256 bits is used for each of the data memories 22 and 23. These data memories 22 and 23 have address terminals ADD.
, a data input terminal D1, a data output terminal DO, and an address terminal ADD of the data memories 22 and 23.
are connected to address output bus AOB via gates G1 and G2, and to address data bus ADB via gates G3 and G4, respectively.

On the other hand, the data input terminals DI of the data memories 22 and 23 are connected to the data output bus D via gates G5 and G6, respectively.
It is connected to the input data bus IDB via gates G7 and G8, and the data output terminal DO
are connected to the data input bus DIB via gates G9 and GIO, respectively, and gates GI1 and GIO are connected to the data input bus DIB via gates G9 and GIO, respectively.
12 to the output data bus ODB. Further, the data memories 22 and 23 are provided with an output write switching terminal RWC, and when a signal is applied to this switching terminal RWC, data is written, and when no signal is applied, data is read. It is about to be done. The strobe signal DOS output from the arithmetic processing unit 21 and the write command signal lOW output from the data exchange circuit 24 are applied to the switching terminals RWC of the data memories 22 and 23, respectively, and the AND gates AG1, AG3, AND gate AG2, It is designed to be given via AG4.
Next, gates GI to GI2 and AND gates AGI to AG4
The control circuit that controls the opening and closing of the will be explained.

The address decoder 25 constitutes a timing signal generating means that outputs a signal at predetermined time intervals in synchronization with the execution of a program.
A timing signal is output every time the address data output from the address data becomes zero. Therefore, the third
As shown in FIG. b, the sequence program stored in the program memory 31 is executed once by the arithmetic processing unit 30, and a timing signal is output every time the sequence program returns to address zero. The timing signal outputted from the address decoder 25 is applied to the trigger terminal T of the flip-flop FFI and the set terminal S of the flip-flops FF3 and FF4 in the data exchange circuit 24. Flipflop FFI is J
, the input terminals J and K of the K-type flip-flop are both /
・It is maintained at the same level. Therefore, the signal is inverted every time a timing signal is applied to the terminal T, and signals are alternately output from the two output terminals, the set output terminal Q and the set output terminal Q. The signals output from these output terminals Q and Q are given to the input states of OR gates OG1 and OG2, respectively.
Gate control signals SC and RC are outputted from the output terminals of the circuit. Of these gate control signals SC and RC, the gate control signal SC is the gate G
I, G4, G5, G8, G9, GI2 and AND gate A
The gate control signal RC is applied to gates G2, G3, G6, GI0, G7, GII and AND gates AG2 and AG3. Therefore, in a program execution cycle in which the flip-flop FFI is set, the data memory 22 is connected to the bus line on the arithmetic processing section 21 side, and the data memory 23
is connected to the bus line on the input/output units 11 and 12 side. The data memory 22 is switched between writing and reading by the strobe signal DOS from the arithmetic processing section 21, and the writing and reading of the data memo IJ 23 is switched by the write command signal lOW from the data exchange circuit 24. On the other hand, in a program execution cycle in which the flip-flop FFI is reset, contrary to the above case, the data memory 23 is connected to the bus line on the arithmetic processing unit 21 side, and the bus line on the input/output unit 11, 12 side is connected to the data memory 23. A data memory 22 is connected to. Then, the data memory 23 is controlled to start writing by a signal from the arithmetic processing section, and the data memory 22 is controlled to start writing by a signal from the data exchange circuit 24. The flip-flop FF2 is provided to store the initial states of the input/output elements sent from the input/output units 11 and 12 in both the data memories 22 and 23 prior to execution of the sequence program. It is set by the initial signal IRS outputted from the device 30, and reset by the signal outputted from the AND gate AG5 of the data exchange circuit 24.

A signal output from the set output terminal Q of this flip-flop FFS is applied to both input terminals of OR gates OG1 and OG2. Therefore, when the flip-flop FF2 is set by the initial signal S from the arithmetic processing unit 30, the gate control signals SC and RC are sent from both OR gates OG1 and OG2.
is now output, and the gates GI to GI2 and the AND gates AGI to AG4 are completely opened. Furthermore, at this time,
No data is output from the arithmetic processing unit 30, the data output terminal and address data terminal of the arithmetic processing unit 30 are held in a high impedance state, and the strobe signal DOS is also not output. Therefore, both data memories 22 and 23 are connected to input/output unit 1
It is connected to the bus lines on the 1 and 12 sides, and outputs address data that changes sequentially from zero to the address data bus ADB, and AND gates AG2 and AG
By applying the write command signal lOW to the input terminal 4, the initial states of the input/output elements connected to the input/output units 11 and 12 can be written to both the data memories 22 and 23. Next, the initial states of the input/output elements as described above are written prior to the start of sequence control, and during sequence control, the initial states of the input/output elements written by the arithmetic processing unit 30 are written in each program execution cycle. The data exchange circuit 24 which transfers the on/off signal to the output unit 12 and also writes the on/off information sent from the input unit 11 into the data memory will be described.

This data exchange circuit 24 includes a clock generation circuit 34, an input/output address counter 35, and flip-flops FF3 and F.
F4, AND gate AG5, AG6, OR gate OG6
, OG7, and the count value of the input/output address counter 35 is output to the address data bus ADB as address data for specifying addresses of the input/output units 11, 12 and data memories 22, 23. . This input/output address counter 35 is a 32-ary counter corresponding to the storage areas of the data memories 22 and 23, and increments every time a step pulse outputted from the clock generation circuit 34 is applied via the AND gate AG6.
Change the count value. When the count value reaches 32, a carry signal CAR is output to reset the count value to zero. In addition, flip-flop FF3 is
It controls opening and closing of AND gate AG6, and is set by a timing signal output from address decoder 25 and reset by a signal from AND gate AG5. This fritsubflop F
The signal from the set output terminal Q of F3 is applied together with the signal from the set output terminal Q of flip-flop FF2 to the other input terminal of AND gate AG6 via OR gate OG6. Therefore, while either flip-flop FF2 or FF3 is set, the input/output address counter 35 is incremented in synchronization with the step clock, and the address data output to the address data bus ADB is changed. flip flop F
F4 controls the input and writing of the data memories 22 and 23, and the set terminal S of this flip-flop FF4 is supplied with a timing signal output from the address decoder 25, and the reset terminal R
is supplied with a carry signal CAR outputted from the input/output address counter 35 and an initial signal IRS from the arithmetic processing unit 30 via an OR gate OG7.

The signal output from the set terminal Q of flip-flop FF4 is given to the input/output units 11 and 12 as a strobe signal SS, and the signal output from the reset output terminal Q is a write command signal lO.
It is provided as W to AND gates AG2 and AG4. Therefore, when the initial signal IRS is output from the arithmetic processing unit 30, the flip-flop FF4 is reset at the same time as the flip-flop FF2 is set, and the write command signal lOW is sent out, but the timing signal is not given from the address decoder 25. In this case, the flip-flop 4 is initially set and the strobe signal SS is sent out, and the input/output address counter 3
When the carrier IJ-signal CAR is output from 5, it is reset and the write command signal lOW is output. Further, the signal from the reset output terminal Q of the flip-flop FF4 is applied to the input terminal of the AND gate AG5 together with the carry signal CAR output from the input/output address counter 35, so that the flip-flop FF4 is in a reset state. When the carry signal CAR is output, a signal is output from the AND gate AG5. FIG. 2 shows the data memories 22, 23 and the input/output unit 11,
This is a flowchart for explaining the data exchange operation performed with 12. The data exchange operation will be explained along this flowchart.

Now, when the sequence controller main body 20 is powered on, an initial signal IRS is sent from the arithmetic processing unit 30, flip-flop FF2 is set, and flip-flop FF4 is reset. When flip-flop FF2 is set, flip-flop F
A signal is output from the set output terminal Q of F2, and gate control signals SC and R are output from OR gates OG1 and 002, respectively.
C is sent.

As a result, all gates GI to GI2 are opened, and both data memories 22 and 23 are connected to input/output units 11, 12.
It is connected to the side bus lines ADB, ODB, and mB. At the same time, AND gates AGI to AG4 are also opened. On the other hand, the set output terminal Q of flip-flop FF2
Since the signal output from is applied to the input state of AND gate AG6 via OR gate OG6, the step clock from clock generation circuit 34 is applied to input/output address counter 35, and input/output address counter 35 The count value is incremented sequentially starting from zero.

Furthermore, when the flip-flop FF4 is reset, a write command signal lOW is sent from the reset output terminal Q, and this write command signal lOW is sent to the AND gate A.
It is applied to both data memories 22 and 23 via G2 and AG4. When the count value of the input/output address counter 35 is incremented, the input/output units 11 and 12 are designated in order from the stolen address, and the on/off state of the input/output elements connected to the designated input/output units 11 and 12 is changed. is output to the input data bus IDB as on/off information, and this on/off information is applied to the data input terminals DI of the data memories 22, 23 via gates G7, G8, respectively.

On the other hand, since the address data output from the input/output address counter 35 is applied to the address terminals ADD of the data memories 22, 23 via the gates G3, G4, the input/output units 11, 12 are selected in order from address zero. At the same time, storage areas in the data memories 22 and 23 are also selected in order from the koto address. Since the write command W is given to the data memories 22 and 23,
The on/off information of the selected input/output units 11, 12 is written in the storage areas of the data memories 23, 23 corresponding to the selected input/output units 11, 12 in accordance with the location number. When all the on/off information from the input/output units 11, 12 is written into the data memories 22, 23 and the count value of the input/output address counter 35 reaches 32, the input/output address counter 35 outputs a carry signal CAR.

Then, a signal is output from the AND gate AG5, the flip-flop FF2 is reset, and the set output terminal Q
The signal will no longer be output. As a result, the transmission of gate control signals SC and RC is stopped, and all gates GI to G12 and AND gates AGI to AC4 are closed. Furthermore, the AND gate AG6 is closed, and the input/output address counter 35 stops incrementing with the calculated value being zero. On the other hand, the signal output from AND gate AG5 is
0 is also given, so the arithmetic processing unit 30 has the initial state of the input/output element as the data memory 22, 2.
It detects that the program has been written to 3 and starts writing the sequence program. To propose a sequence program,
Since it starts from address zero of program memory 3-1,
When the sequence program is started, a timing signal is output from the address decoder 25, and this timing signal causes the trigger of the flip-flop FFI to be output to the terminal T.
is applied to the set terminals S of flip-flops FF3 and FF4.

When a signal is applied to the terminal T of the flip-flop FFI, the flip-flop FFI is inverted.

For example, if the initial state of the flip-flop FFI is a reset state, it is inverted and becomes a set state, and a signal is output from the set output terminal Q. As a result, the gate control signal SC is output from the OR gate OGI,
Gates GI, G4, G5, G9, G8, GI2 and AND gates AG1, AG4 are opened. As a result, the arithmetic processing device 30 can send and write data to the data memory 22, and the data exchange device 2
4 becomes able to read and write data to the data memory 23. On the other hand, flip-flop FF3
When is set, a signal is applied to AND gate AG6 via OR gate OG6, and the count value of input/output address counter 35 is sequentially incremented from zero.

Furthermore, since flip-flop FF4 is set at the same time, strobe signal SS is output to input/output units 11 and 12. As a result, the on/off signal stored in the data memory 23 is outputted to the drop address or another item number and transferred to the input/output units 11 and 12. In this case, since the initial state of the input/output unit is stored in the data memory 23, the on/off state of the output element does not change. In this way, the on/off signals are transferred, and when all 32 words of on/off signals stored in the data memory 23 are transferred, the count value of the input/output address counter 35 returns from 31 to zero. A carry signal CAR is output. Then, the count value of the input/output address counter 35 is again incremented from zero in synchronization with the increment clock. On the other hand, the input/output address counter 35
When the carry signal CAR is output from the flip-flop FF4, the flip-flop FF4 is reset.
The oath signal lOW is output from F4, and the data memory 23
will perform a write operation. As a result, the input/output units 11, 12 are selected from the zero address to the prime number, and the on/off information from the selected input/output units 11, 12 is stored in the storage area corresponding to the selected input/output units 11, 12. It will be written. When writing of the on/off information is completed and a carry signal CAR is sent from the input/output address counter 35, a signal is output from the AND gate AG5 and the flip-flop FF3 is reset. As a result, AND gate AG6 is closed and the input/output address counter 35 stops incrementing. Note that, as shown in FIGS. 3e and 3f, the data exchange described above is completed faster than when the arithmetic processing unit 30 executes the sequence program once, and waits until the timing signal is sent from the address decoder 25. state.

The arithmetic processing unit 301 has one sequence program.
When the sequence program is executed once again and the sequence program is started again from address zero in the program memory 31, a timing signal is sent from the address decoder 25.

As a result, flip-flop FFI is inverted and becomes a reset state, and flip-flops FF3 and FF4 are set again. When the flip-flop FFI enters the reset state, the gate control signal RC is output instead of the gate control signal SC, and the gates GI, G4,
Gates G2, G3, instead of G5, G9, G8, GI2,
G6, GI0, G7, GII are opened, and gate A
AND gates AG2 and AG3 are opened in place of G1 and AG4. As a result, the data memory 23 is accessed by the arithmetic processing unit 301, and the data memory 22 is accessed by the data exchange circuit 24. The data exchange circuit 24 is a flip-flop FF.
3. By setting FF4, in the same way as in the previous case, the on/off signal written by the arithmetic processing unit 3 in the previous cycle is extracted from the data memory 22 and transferred to the input/output units 11 and 12. When the transfer is completed, the on/off information of the input/output elements sent from the input/output units 11 and 12 is written into the data memory 22.

Similarly, each time the sequence program is executed once by the three arithmetic processing units, the data memory valid for the three arithmetic processing units and the data memory valid for the data exchange circuit 24 are changed. Can be switched. Thereby, the on/off signal output from the arithmetic processing unit 30 and the on/off information from the input/output units 11 and 12 are exchanged via the data memories 22 and 23. In this way, in the sequence controller of the present invention, there is no need to cause the arithmetic processing section to operate intermittently, and the arithmetic processing section of a sequence controller other than the remote 10 type can be used.

Further, in the above embodiment, the on/off signal written in the data memory is transferred to all input/output units without distinction between input/output units, and after the transfer of this on/off signal is completed, all input/output units Since I am trying to write the on/off information of the input/output element connected to
The input/output unit can be configured with an identification circuit that identifies whether the selected unit is an input unit or an output unit, or by separating the address for connecting the input unit and the address for connecting the output unit. Data can be exchanged between the data memory and the input/output unit without any need for identification, and the ratio of the input/output units can be changed and the arrangement can be changed freely. It becomes possible. In the above embodiment, the data memory is switched and data is exchanged each time the arithmetic processing unit 3 executes the sequence program once.
If data exchange is to be completed in a short time, the data memory may be switched multiple times while the sequence program is executed once, so that data is exchanged each time the data memory is switched. If data exchange takes time, data may be exchanged by switching the data memories each time the sequence program is executed a plurality of times.

FIG. 4 shows another embodiment of the present invention, in which the output unit 12 of this embodiment has an input data bus ID that stores the on/off states of flip-flops that store the energization and non-energization of output elements.
A feedback circuit for outputting to B is not provided.

When such an output unit 12 is used, when writing on/off data from the input/output units 11 and 12 to the data memories 22 and 23, the all-0 empty information sent from the output unit 12 is transferred to the data memories 22 and 23. 23, and the on/off signal written by the arithmetic processing unit 30 is invalidated. Therefore, only the on/off information from the input unit 11 is stored in the data memories 22, 23, and the arithmetic processing unit 30 cannot test the on/off states of the output elements. Therefore, in the sequence control of this example,
The arithmetic processing unit 21 is provided with an output data memory 40 for storing on/off states of output elements.

This data memory 40 is a semiconductor memory with the same capacity as the data memories 22 and 23.
The address terminal ADD of is connected to the address output bus AOB, and the data input terminal DI is connected to the data output bus DOB. On the other hand, the data output terminal DO is connected to the logic gate 41 along with the data input bus DIB, and the output of this logic gate 41 is applied to the data input terminal of the arithmetic processing unit 30. This logic gate 41
'The logic gate 41 calculates the logical sum between each bit of two input data and outputs the result.
The on/off information from the output element and the on/off information of the output element stored in the output data memory 40' are output. This makes it possible to test the on/off states of the output elements of the three arithmetic processing units. Further, as in this embodiment, when there is no feedback from the output unit 12, data between the data memories 22, 23 and the input/output units 11, 12 is transferred while the sequence program is executed once. If the exchange is performed more than once, output unit 1
There is a risk that all output elements will be inactive due to the all-zero empty information fed back from 2. For this reason, the period for switching the data memories 22 and 23 and exchanging data must be longer than the time required for executing the sequence program once. Note that although the above embodiment was an embodiment in which the input/output units 11 and 12 were not identified, a circuit that can identify the input/output units 1 and 12 is provided, and the selected unit is the input unit 1.
1, the on/off information from the input unit 11 is written to the data memories 22 and 23, and when the selected unit is the output unit 12, the on/off information from the input unit 11 is written to the data memory 2.
The on/off signals No. 2 and 23 may be transferred to the output unit.

In this case, data can be exchanged by scanning the data memories 22 and 23 once, and data can be exchanged in a short time. Furthermore, if a general input/output unit other than the remote 10 is connected to the data buses AOB, DIB, and DOB of the arithmetic processing unit 30, the remote 10 and the general 10 can be controlled simultaneously by one arithmetic processing unit. Furthermore, in the above embodiment, the data memory 22
, 23 and the input/output units 11 and 12 is performed in parallel, but it may also be performed in serial. As described above, in the sequence controller of the present invention, two sets of data memories are provided, and these two sets of data memories are provided.
Since the two data memories are connected alternately and reciprocally to the input/output bus line of the processing unit and the input/output unit, on/off data exchange between the data memory and the input/output unit is easy. This has the advantage that it can be performed at all times except when switching memories, and even when there is a large amount of on/off information to be exchanged, the data can be exchanged in a short time.

Further, in the present invention, on/off signals corresponding to all input/output elements are sent from the data memory to the input/output unit, and after this, on/off information of all the input/output elements is read from the input/output unit and stored in the data memory. Since it is equipped with a writing data exchange means, the on/off information written by the arithmetic processing unit to the data memory is not destroyed by the on/off information stored from the input/output unit before being transferred to the input/output unit. There is no need to determine whether the unit connected to each address is an input unit or an output unit and transfer on/off information.

Therefore, there is an advantage that the input unit and the output unit can be connected to any address in any ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a flowchart for explaining the data exchange operation of the sequence controller shown in FIG. 1. FIG. 3 is a time chart showing changes in data processing performed on the data memories 22 and 23, and FIG. 4 is a block diagram showing a second embodiment of the present invention. 11... Input unit, 12... Output unit, 21... Arithmetic processing unit, 22, 23... Data memory, 24...
...Data exchange circuit, 24...Address data, 30...Arithmetic processing unit, 31...
...Program memory, 32...Program counter,
34...Clock generation circuit, 35...
Input/output address counter, 40...output data memory,
41...Logic gate, AGI~AG6...
AND gate, FFI~FF4...Flip-flop, GI~GI2...gate, OGI~OG7...
Orgate. Diagram below: Diagram 2 - Diagram below: Dimensions:

Claims (1)

[Claims] 1. An arithmetic processing unit that executes a sequence program stored in a program memory, an input/output unit to which input elements such as limit switches and output elements such as relays are connected, and a connection between this input/output unit and the arithmetic processing unit. In a sequence controller comprising a data memory provided and a data exchange means for exchanging on/off information between the data memory and the input/output unit, an input/output bus line connected to the arithmetic processing section; two sets of data memories each having a storage area corresponding to each address of an input/output element connected to the input/output unit;
a timing signal generating means for outputting a signal at a time interval longer than at least the reading execution time of the sequence program by the arithmetic processing section; and a gate switching by the signal from the timing signal generating means so that one data memory is in front of the other. During the period when the other data memory is connected to the input/output bus line, the other data memory is connected to the input/output unit, and during the period when the other data memory is connected to the input/output bus line, the one data memory is connected to the input/output unit. memory switching means for connecting to the input/output unit, and sending on/off signals corresponding to all input/output elements from the data memory to the input/output unit each time the data memory is switched; A sequence controller comprising: data exchange means for reading on/off information of input/output elements from the input/output unit and writing it into the data memory.