KR970050868A - Parallel CRC decoder - Google Patents

Parallel CRC decoder Download PDF

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Publication number
KR970050868A
KR970050868A KR1019950061867A KR19950061867A KR970050868A KR 970050868 A KR970050868 A KR 970050868A KR 1019950061867 A KR1019950061867 A KR 1019950061867A KR 19950061867 A KR19950061867 A KR 19950061867A KR 970050868 A KR970050868 A KR 970050868A
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South Korea
Prior art keywords
parallel
register
unit
register unit
predetermined amount
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KR1019950061867A
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Korean (ko)
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KR0169362B1 (en
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주태식
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김광호
삼성전자 주식회사
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Publication of KR970050868A publication Critical patent/KR970050868A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G11B2020/1843—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using a cyclic redundancy check [CRC]

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

이 발명은 병렬 CRC 디코더에 관한 것으로, 인에이블 신호와 클럭신호를 입력받고, 일정량의 비트 단위의 데이터를 병렬로 입력받아 나눗셈 연산을 하기 위한 제1레지스터부와, 인에이블신호와 클럭신호를 입력받고, 상기 제1레지스터부의 출력신호를 병렬로 입력받아 나눗셈 연산을 하기 위한 제2레지스터부와; 상기 제2레지스터부에서 출력되는 일정량의 비트의 데이터를 병렬로 입력받아, 제1레지스터부가 16비트 병렬 연산이 가능하도록 하기 위한 제1논리연산부와; 상기 제2레지스터부에서 출력되는 일정량의 비트의 데이터를 병렬로 입력받아, 제2레지스터부가 일정량의 비트 병렬 연산이 가능하도록 하기 위한 제2논리연산부와; 상기 제1레지스터부와 제2레지스터부에서 출력되는 모든 신호들을 입력받아 모든 비트 전체가 '0'일 때, 에러가 없다는 출력을 하고, 그렇지 않을 때는 에러가 있다는 출력을 하기 위한 에러출력부를 포함하여 구성되어, EDC 디코딩에 많은 시간이 걸리던 것을 대폭 감소시킨 병렬 CRC 디코더에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel CRC decoder, comprising: an enable signal and a clock signal, a first register part for receiving a predetermined amount of bit unit data in parallel and performing a division operation; and an enable signal and a clock signal. A second register unit configured to receive the output signal of the first register unit in parallel and perform a division operation; A first logic operation unit configured to receive a predetermined amount of data from the second register unit in parallel, and to allow the first register unit to perform 16-bit parallel operation; A second logic operation unit configured to receive a predetermined amount of bit data output from the second register unit in parallel, and allow the second register unit to perform a predetermined amount of bit parallel operation; Including an error output unit for receiving all signals output from the first register unit and the second register unit and outputting no error when all bits are '0', otherwise outputting an error. The present invention relates to a parallel CRC decoder which greatly reduces the time required for the EDC decoding.

Description

병렬 CRC 디코더Parallel CRC decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 이 발명의 실시예에 따른 병렬 CRC 디코더의 구성도.4 is a block diagram of a parallel CRC decoder according to an embodiment of the present invention.

제5도는 이 발명의 실시예에 따른 병렬 CRC 디코더 내의 제1레지스터의 상세회로도.5 is a detailed circuit diagram of a first register in a parallel CRC decoder according to an embodiment of the present invention.

제6도는 이 발명의 실시예에 따른 병렬 CRC 디코더 내의 제2레지스터의 상세회로도.6 is a detailed circuit diagram of a second register in a parallel CRC decoder according to an embodiment of the present invention.

Claims (4)

인에이블신호와 클럭신호를 입력받고, 일정량의 비트 단위의 데이터를 병렬로 입력받아 나눗셈 연산을 하기 위한 제1레지스터부와, 인에이블신호와 클럭신호를 입력받고, 상기 제1레지스터부의 출력신호를 병렬로 입력받아 나눗셈 연산을 하기 위한 제2레지스터부와; 상기 제2레지스터부에서 출력되는 일정량의 비트의 데이터를 병렬로 입력받아, 제1레지스터부가 16비트 병렬 연산이 가능하도록 하기 위한 제1논리연산부와; 상기 제2레지스터부에서 출력되는 일정량의 비트의 데이터를 병렬로 입력받아, 제2레지스터부가 일정량의 비트 병렬 연산이 가능하도록 하기 위한 제2논리연산부와; 상기 제1레지스터부와 제2레지스터부에서 출력되는 모든 신호들을 입력받아 모든 비트 전체가 '0'일 때, 에러가 없다는 출력을 하고, 그렇지 않을 때는 에러가 있다는 출력을 하기 위한 에러출력부를 포함하여 구성되어짐을 특징으로 하는 병렬 CRC 디코더.Receiving an enable signal and a clock signal, receiving a predetermined amount of bit unit data in parallel, a first register unit for performing a division operation, an enable signal and a clock signal, and outputting the output signal of the first register unit. A second register unit configured to receive a parallel input and perform a division operation; A first logic operation unit configured to receive a predetermined amount of data from the second register unit in parallel, and to allow the first register unit to perform 16-bit parallel operation; A second logic operation unit configured to receive a predetermined amount of bit data output from the second register unit in parallel, and allow the second register unit to perform a predetermined amount of bit parallel operation; Including an error output unit for receiving all signals output from the first register unit and the second register unit and outputting no error when all bits are '0', otherwise outputting an error. Parallel CRC decoder characterized in that the configuration. 제1항에 있어서, 상기한 제1레지스터부는 16비트의 데이터를 병렬로 입력받는 것을 특징으로 하는 병렬 CRC 디코더.The parallel CRC decoder of claim 1, wherein the first register receives 16 bits of data in parallel. 제1항에 있어서, 상기한 제1레지스터부는 병렬 데이터 처리가 가능하도록, x0~x15레지스터에서는 입력 메인 데이터와 각 자리수별로 익스클루시브 오아 연산을 하여 레지스터에 입력하고, x16~x31레지스터에서는 위의 결과와 x0~x31레지스터 출력값을 각각 익스클루시브 오아 연산하여 입력하는 것을 특징으로 하는 병렬 CRC 디코더.2. The method of claim 1, wherein the first resistor portion in, x 0 ~ x 15 register to allow parallel data processing to the input main data and the exclusive Iowa operation for each digit and the input to the register, x 16 ~ x 31 The register is a parallel CRC decoder characterized by inputting the result of the above and the output value of the register 0 0 ~ x 31 , respectively. 제1항에 있어서, 상기한 제1레지스터부 및 제2레지스터부는 병렬레지스터 및 익스클루시브 오아 게이트를 포함하여 구성되어 짐을 특징으로 하는 병렬 CRC 디코더.The parallel CRC decoder of claim 1, wherein the first register portion and the second register portion comprise a parallel register and an exclusive oar gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061867A 1995-12-28 1995-12-28 Parallel crc decoder KR0169362B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010057408A (en) * 1999-12-22 2001-07-04 박종섭 Apparatus for commputation cyclic redundancy codes
KR100505566B1 (en) * 1997-07-29 2005-11-08 삼성전자주식회사 Parallel Circulation Check Method for Subcode Q Data

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101286238B1 (en) 2007-08-01 2013-07-15 삼성전자주식회사 Data parallelizing receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505566B1 (en) * 1997-07-29 2005-11-08 삼성전자주식회사 Parallel Circulation Check Method for Subcode Q Data
KR20010057408A (en) * 1999-12-22 2001-07-04 박종섭 Apparatus for commputation cyclic redundancy codes

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