KR970029016A - Method and circuit for finding the remainder in binary arithmetic processing - Google Patents

Method and circuit for finding the remainder in binary arithmetic processing Download PDF

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Publication number
KR970029016A
KR970029016A KR1019950041907A KR19950041907A KR970029016A KR 970029016 A KR970029016 A KR 970029016A KR 1019950041907 A KR1019950041907 A KR 1019950041907A KR 19950041907 A KR19950041907 A KR 19950041907A KR 970029016 A KR970029016 A KR 970029016A
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South Korea
Prior art keywords
remainder
address
significant bit
inversion
jets
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KR1019950041907A
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Korean (ko)
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KR0164728B1 (en
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최성업
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김광호
삼성전자 주식회사
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Priority to KR1019950041907A priority Critical patent/KR0164728B1/en
Publication of KR970029016A publication Critical patent/KR970029016A/en
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Publication of KR0164728B1 publication Critical patent/KR0164728B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

본 발명은 2진 연산처리에 관한 것으로, 모든 비트가 "1"로 구성된 젯수로 나눗셈을 수행하는 경우 나머지를 고속으로 구할수 있게 함과 동시에 하드웨어 구성을 용이하게 하도록 하는 나머지를 구하는 방법 및 회로에 관한 것이다.The present invention relates to binary arithmetic processing, and in the method and circuit for obtaining the remainder which makes it possible to obtain the remainder at high speed while facilitating the hardware configuration when performing division by the number of jets of all bits "1". It is about.

종래에는 나머지를 산출하는 경우 대부분 일반화된 나눗셈식을 이용함으로 인하여 나머지만을 구하는 데에있어 많은 시간과 노력이 소요되며 하드웨어 구성이 용이하지 않다는 문제점이 있다.Conventionally, when calculating the remainder, it takes a lot of time and effort to obtain the remainder only by using a generalized division formula, and there is a problem that hardware configuration is not easy.

본 발명은 모든 비트가 "1"로 구성된 젯수로 나눗셈을 수행하는 경우 나머지를 고속으로 구할수 있고 하드웨어 구성을 용이하게 할수 있으므로 나머지를 계산하여 신호처리를 수행하는 시스템에 유용하게 적용할 수 있다.The present invention can be usefully applied to a system that performs signal processing by calculating the remainder since the remainder can be obtained at high speed and the hardware configuration can be easily performed when performing division by the number of jets in which all bits are "1".

Description

2진 연산처리에 있어서의 나머지를 구하는 방법 및 회로Method and circuit for finding the remainder in binary arithmetic processing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에서의 "1111"로 나눈 나머지를 계산하기 위한 반전-쉬프트 모듈을 도시한 도면,3 shows an inversion-shift module for calculating the remainder divided by " 1111 "

제4도는 본 발명에서의 연속되는 비트 "1"을 갖는 젯수에 대하여 나머지를 계산하는 회로를 도시한 블럭도.4 is a block diagram showing a circuit for calculating the remainder for the number of jets having consecutive bits " 1 " in the present invention.

Claims (2)

2진 연산처리에 있어서의 나머지를 구하는 방법에 있어서, 모든 연속적인 비트가 "1"인 젯수와 소정 피젯수의 최상위비트 "1"이 일치하도록 자리수를 정렬하는 제1과정과; 상기 젯수와 피젯수의 최상위비트 이후에 존재하는 값이 상호간에 상이하면 상기 피젯수의 마지막 비트를 반전시켜 나머지값의 최하위비트를 얻고 1비트 쉬프트하여 나머지값의 최상위비를 얻는 제2과정과; 상기 젯수와 피젯수의 최상위비트 이후에 존재하는 값이 상호간에 일치하면 인버팅하여 나머지를 구하는 제3과정을 포함하는 것을 특징으로 하는 2진 연산처리에 있어서의 나머지를 구하는 방법.A method for finding the remainder in binary arithmetic processing, comprising: a first step of aligning digits such that the number of jets in which all consecutive bits are "1" and the most significant bit "1" of the predetermined pidget number match; A second step of obtaining the least significant bit of the remaining value by shifting the last bit of the number of the pidget number and shifting by one bit if the value present after the most significant bit of the jet number and the pidget number is different from each other; And a third step of inverting and calculating a remainder if the values existing after the most significant bit of the jet number and the pidget number coincide with each other. 2진 연산처리에 있어서의 나머지를 구하는 회로에 있어서, 제어신호에 따라 어드레스를 출력하는 어드레스 제어부와; 방전-쉬프트 연산처리 동작을 수행하여 산출된 나머지 값을 출력하는 반전-쉬프트 모듈과; 상기 반전-쉬프트 모듈을 제어하여 모든 연속적인 비트가 "1"인 젯수와 소정 피젯수의 최상위비트 "1"이 일치하도록 처리하여 주는 제어동작을 수행함과 동시에 상기 어드레스 제어부의 어드레스 출력동작을 제어하는 주제어부와; 입력되는 2진 데이타를 상기 어드레스 제어부로부터 인가되는 어드레스에 따라 순서대로 상기 반전-쉬프트 모듈측에 출력하는 래치와; 상기 반전-쉬프트 모듈로부터 출력되는 비트중의 일부를 상기 래치측으로 귀환시키는 루프부를 포함하는 것을 특징으로 하는 2진 연산처리에 있어서의 나머지를 구하는 회로.A circuit for finding the remainder in binary arithmetic processing, comprising: an address control section for outputting an address in accordance with a control signal; An inversion-shift module for outputting the remaining value calculated by performing a discharge-shift operation processing operation; By controlling the inversion-shift module to perform a control operation to process the number of jets of all consecutive bits "1" and the most significant bit "1" of the predetermined number of jets, and to control the address output operation of the address control unit Subject fisherman; A latch for outputting input binary data to the inversion-shift module side in order according to an address applied from the address control section; And a loop portion for returning a part of the bits output from the inversion-shift module to the latch side. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950041907A 1995-11-17 1995-11-17 A circuit of obtaining the residue of binary calculation KR0164728B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950041907A KR0164728B1 (en) 1995-11-17 1995-11-17 A circuit of obtaining the residue of binary calculation

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Application Number Priority Date Filing Date Title
KR1019950041907A KR0164728B1 (en) 1995-11-17 1995-11-17 A circuit of obtaining the residue of binary calculation

Publications (2)

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KR970029016A true KR970029016A (en) 1997-06-26
KR0164728B1 KR0164728B1 (en) 1999-01-15

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