KR970012117A

KR970012117A - Programmable counter using Johnson counter

Info

Publication number: KR970012117A
Application number: KR1019950027241A
Authority: KR
Inventors: 이보현
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-29
Filing date: 1995-08-29
Publication date: 1997-03-29

Abstract

본 발명은 프로그램어블 카운터에 관한 것으로서, 특히 제어신호를 입력하는 제어 레지스터; 제1클럭신호를 입력하는 제1입력수단; 제어 레지스터의 제1비트에 응답하여 제2클럭신호를 입력하는 입력수단; 제어 레지스터의 제2 및 제3비트에 응답하여 상기 제1 및 제2클럭신호를 선택하는 제1 및 제2선택수단; 데이타를 디코딩하는 제1 및 제2디코더; 제어 레지스터의 제4비트에 응답하여 선택된 클럭신호를 상기 제1디코더의 출력과 상기 제어 레지스터의 제6비트에 응답하여 계수하는 제1존슨 카운터; 제어 레지스터의 제5비트에 응답하여 선택된 클럭신호를 상기 제2디코더의 출력과 상기 제어 레지스터의 제7비트에 응답하여 계수하는 제2존슨 카운터; 및 제1 및 제2존슨 카운터의 출력을 상기 제어 레지스터의 제8비트에 응답하여 선택하는 제3선택수단을 구비한다.The present invention relates to a programmable counter, in particular a control register for inputting a control signal; First input means for inputting a first clock signal; Input means for inputting a second clock signal in response to a first bit of the control register; First and second selection means for selecting the first and second clock signals in response to second and third bits of a control register; First and second decoders for decoding data; A first Johnson counter that counts a clock signal selected in response to a fourth bit of a control register in response to an output of the first decoder and a sixth bit of the control register; A second Johnson counter that counts a clock signal selected in response to a fifth bit of a control register in response to an output of the second decoder and a seventh bit of the control register; And third selecting means for selecting outputs of the first and second Johnson counters in response to the eighth bit of the control register.

따라서, 본 발명에는 존슨 카운터를 사용함으로써, 회로구성을 보다 간단하게 할 수 있다.Therefore, the circuit configuration can be made simpler by using the Johnson counter in the present invention.

Description

Programmable Counters Using Johnson Counters

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 프로그램어블 카운터의 타이머/카운터 블럭의 구성도.2 is a block diagram of a timer / counter block of a programmable counter according to the present invention.

Claims

A control register for inputting a control signal; First input means for inputting a first clock signal; Second input means for inputting a second clock signal in response to a first bit of the control register; First and second selection means for selecting the first and second clock signals in response to second and third bits of the control register; First and second decoders for decoding data; A first Johnson counter that counts a clock signal selected in response to a fourth bit of the control register in response to an output of the first decoder and a sixth bit of the control register; A second Johnson counter that counts a clock signal selected in response to a fifth bit of the control register in response to an output of the second decoder and a seventh bit of the control register; And third selecting means for selecting outputs of the first and second Johnson counters in response to an eighth bit of the control register.

※ Note: The disclosure is based on the initial application.