KR960027376A - Run processing circuit in run length decoding (RLD) - Google Patents

Run processing circuit in run length decoding (RLD) Download PDF

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Publication number
KR960027376A
KR960027376A KR1019940034108A KR19940034108A KR960027376A KR 960027376 A KR960027376 A KR 960027376A KR 1019940034108 A KR1019940034108 A KR 1019940034108A KR 19940034108 A KR19940034108 A KR 19940034108A KR 960027376 A KR960027376 A KR 960027376A
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KR
South Korea
Prior art keywords
run
predetermined
request signal
output
predetermined bit
Prior art date
Application number
KR1019940034108A
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Korean (ko)
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KR0153967B1 (en
Inventor
조영철
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019940034108A priority Critical patent/KR0153967B1/en
Publication of KR960027376A publication Critical patent/KR960027376A/en
Application granted granted Critical
Publication of KR0153967B1 publication Critical patent/KR0153967B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Processing (AREA)

Abstract

본 발명은 2개의 런(Run)과 레벨(Level)을 입력으로 받을 때 런의 콘트롤을 용이하게 하는 RLD에서의 런처리 회로에 관한 것으로, 이를 해결하기 위해 소정 비트의 크기를 갖는 런을 입력받아 소정비트씩 각각 디코딩한 후 병렬로 출력하여 소정 클럭마다 쉬프트시켜 요구 신호를 출력하는 런처리부가 소정개 구비되는 런처리 수단; 소정 비트의 크기를 갖는 레벨을 소정개 입력받고 상기 런처리 수단에서 출력되는 요구 신호에 따라 상기 소정개의 레벨 또는 '0'의 값을 선택 출력하는 멀티플렉서를 포함하도록 구성된다.The present invention relates to a run processing circuit in an RLD that facilitates control of a run when two run and level inputs are input. To solve this problem, the present invention receives a run having a predetermined bit size. A run processing unit which includes a predetermined run processing unit which decodes each of the predetermined bits and outputs them in parallel and shifts each predetermined clock to output a request signal; And a multiplexer for receiving a predetermined level having a predetermined bit size and selectively outputting the predetermined level or a value of '0' according to a request signal output from the run processing means.

Description

런 길이 복호화(RLD)에서의 런처리 회로Run processing circuit in run length decoding (RLD)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 RLD에서의 런처리 회로를 나타낸 블럭도, 제4도는 본 발명에 따른 런처리 회로의 전체블럭도.2 is a block diagram showing a run processing circuit in the RLD according to the present invention, and FIG. 4 is an overall block diagram of the run processing circuit according to the present invention.

Claims (2)

소정 비트의 크기를 갖는 런을 입력받아 소정 비트씩 각각 디코딩한 후 각각의 디코딩 출력을 소정 클럭마다 소정 비트씩 쉬프트시키면서 요구 신호를 출력하는 런처리부가 소정개 구비되는 런처리 수단; 소정 비트의 크기를 갖는 레벨을 소정개 입력받고 상기 런처리 수단에서 출력되는 요구 신호에 따라 상기 소정 레벨 또는 '0'의 값을 선택 출력하는 멀티플렉서가 구비됨을 특징으로 하는 RLD에서의 런처리 회로.A run processing unit for receiving a run having a predetermined bit size and decoding each of the predetermined bits, and outputting a request signal while shifting each decoding output by a predetermined bit for each predetermined clock; And a multiplexer for receiving a predetermined level having a predetermined bit size and selectively outputting the predetermined level or a value of '0' according to a request signal output from the run processing means. 제1항에 있어서, 상기 런처리부는 상기 소정 비트의 크기를 갖는 런을 소정 비트씩 각각 디코딩하여 병렬로 출력하는 제1 내지 제3디코더; 상기 각각의 디코더에서 출력되는 소정 비트의 병력 데이타를 소정 클럭마다 소정 비트씩 각각 쉬프트시키는 제1 내지 제3쉬프트 레지스터; 상기 제1 내지 제3쉬프트 레지스터의 출력을 논리조합하여 요구 신호를 출력하는 앤드 게이트로 구성되며, 상기 앤드 게이트에서 출력되는 요구 신호가 1이 되었을 때 런의 카운트가 끝나게 되고, 다음 런과 레벨을 입력받음을 특징으로 하는 RLD에서의 런처리 회로.The apparatus of claim 1, wherein the run processor comprises: first to third decoders for decoding each of the runs having a predetermined size of bits by a predetermined bit and outputting the same in parallel; First to third shift registers for shifting history data of a predetermined bit output by the respective decoders by a predetermined bit for each predetermined clock; And an AND gate configured to logically combine the outputs of the first to third shift registers to output a request signal. When the request signal output from the AND gate becomes 1, the count of the run ends, and the next run and level are changed. Run processing circuit in the RLD characterized by receiving. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034108A 1994-12-14 1994-12-14 Run length decoder KR0153967B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940034108A KR0153967B1 (en) 1994-12-14 1994-12-14 Run length decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940034108A KR0153967B1 (en) 1994-12-14 1994-12-14 Run length decoder

Publications (2)

Publication Number Publication Date
KR960027376A true KR960027376A (en) 1996-07-22
KR0153967B1 KR0153967B1 (en) 1998-12-15

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ID=19401400

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940034108A KR0153967B1 (en) 1994-12-14 1994-12-14 Run length decoder

Country Status (1)

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KR (1) KR0153967B1 (en)

Also Published As

Publication number Publication date
KR0153967B1 (en) 1998-12-15

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