KR910010299A - Bit operation processing circuit of programmable controller - Google Patents

Bit operation processing circuit of programmable controller Download PDF

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Publication number
KR910010299A
KR910010299A KR1019890015874A KR890015874A KR910010299A KR 910010299 A KR910010299 A KR 910010299A KR 1019890015874 A KR1019890015874 A KR 1019890015874A KR 890015874 A KR890015874 A KR 890015874A KR 910010299 A KR910010299 A KR 910010299A
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KR
South Korea
Prior art keywords
data
state
logic
state signal
storage device
Prior art date
Application number
KR1019890015874A
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Korean (ko)
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KR920005228B1 (en
Inventor
허진강
Original Assignee
이경훈
대우중공업 주식회사
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Priority to KR1019890015874A priority Critical patent/KR920005228B1/en
Publication of KR910010299A publication Critical patent/KR910010299A/en
Application granted granted Critical
Publication of KR920005228B1 publication Critical patent/KR920005228B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)

Abstract

내용 없음.No content.

Description

프로그래머블 콘트롤러의 비트연산 처리회로Bit operation processing circuit of programmable controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 제1도의 비트연산 처리회로를 도시한 개략적인 블럭도.2 is a schematic block diagram showing the bit operation processing circuit of FIG. 1 according to the present invention;

제3도는 제2도 본 발명의 비트연산처리회로 동작을 설명하기위한 래더 프로그램도.3 is a ladder program diagram for explaining the operation of the bit operation processing circuit of the present invention.

Claims (1)

사용자가 입력한 연산프로그램을 기억하는 기억장치(20)로 부터 연산명령데이타를 읽어오기위한 어드레스를 디코더하는 프로그램카운터(51)와, 상기 프로그램 카운터(51)에 의해 상기 기억장치(20)로 부터 입력되는 상기 연산 명령데이타를 디코더하여 출력하는 명령어디코더(55)와, 상기 명령디코더(53)로 부터 연산논리데이타와 상기 기억장치(20)로 부터 접점온 상태의 제1상태 신호 또는 오프상태의 제2상태 신호인 접점데이타를 입력하여 순서적으로 비트연산을 행하여 출력하는 연산장치(54)를 포함하는 프로그래머블 콘트롤러의 비트연산 장치에 있어서, 상기 연산장치(54)로 부터 결과치를 입력하고, 상기 명령디코더(53)로 부터 다음상기 연산 논리 데이타를 입력하여 상기 연산논리 데이타가 AND논리이고, 상기 결과치가 상기 제2상태신호인 경우 및 상기 연산 논리데이타가 OR논리이고 상기 결과치가 제1상태신호인 경우, 상기 프로그램 카운터(51)로 스킵 명령을 출력하는 스킵 판단회로(55)를 포함하는 것을 특징으로 하는 프로그래머블 콘트롤러의 비트연산장치.A program counter 51 which decodes an address for reading operation instruction data from a storage device 20 storing a calculation program input by a user, and a program counter 51 from the storage device 20. A command decoder 55 for decoding and outputting the input operation command data; and a first state signal of a contact-on state or an off state of operation logic data from the command decoder 53 and a contact on state from the storage device 20. A bit controller of a programmable controller, comprising: an arithmetic unit 54 for inputting contact data, which is a second state signal, to sequentially perform bit operation and output the bit data, wherein a result value is input from the arithmetic unit 54, and The operation logic data is inputted from the instruction decoder 53 and the operation logic data is AND logic, and the result value is the second state signal. And a skip determination circuit (55) for outputting a skip command to the program counter (51) when the arithmetic logic data is OR logic and the result value is a first state signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890015874A 1989-11-02 1989-11-02 Bit arithmetic circuit for programmable controller KR920005228B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890015874A KR920005228B1 (en) 1989-11-02 1989-11-02 Bit arithmetic circuit for programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015874A KR920005228B1 (en) 1989-11-02 1989-11-02 Bit arithmetic circuit for programmable controller

Publications (2)

Publication Number Publication Date
KR910010299A true KR910010299A (en) 1991-06-29
KR920005228B1 KR920005228B1 (en) 1992-06-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015874A KR920005228B1 (en) 1989-11-02 1989-11-02 Bit arithmetic circuit for programmable controller

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KR (1) KR920005228B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484247B1 (en) * 2000-12-28 2005-04-20 매그나칩 반도체 유한회사 An instruction decoder for a RCI MCU
KR100648178B1 (en) * 2003-05-16 2006-11-24 아주대학교산학협력단 Bit Manipulation Operation Circuit and Method in Programmable Processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484247B1 (en) * 2000-12-28 2005-04-20 매그나칩 반도체 유한회사 An instruction decoder for a RCI MCU
KR100648178B1 (en) * 2003-05-16 2006-11-24 아주대학교산학협력단 Bit Manipulation Operation Circuit and Method in Programmable Processor

Also Published As

Publication number Publication date
KR920005228B1 (en) 1992-06-29

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