KR920004978A - Address Expansion Method Using I / O Function of Microprocessor - Google Patents

Address Expansion Method Using I / O Function of Microprocessor Download PDF

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Publication number
KR920004978A
KR920004978A KR1019900013695A KR900013695A KR920004978A KR 920004978 A KR920004978 A KR 920004978A KR 1019900013695 A KR1019900013695 A KR 1019900013695A KR 900013695 A KR900013695 A KR 900013695A KR 920004978 A KR920004978 A KR 920004978A
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KR
South Korea
Prior art keywords
microprocessor
memory
flip
address
flop
Prior art date
Application number
KR1019900013695A
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Korean (ko)
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KR940009821B1 (en
Inventor
정진언
Original Assignee
정장호
금성정보통신 주식회사
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Priority to KR1019900013695A priority Critical patent/KR940009821B1/en
Publication of KR920004978A publication Critical patent/KR920004978A/en
Application granted granted Critical
Publication of KR940009821B1 publication Critical patent/KR940009821B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음No content

Description

마이크로 프로세서의 입출력 기능을 이용한 어드레스 확장법Address Expansion Method Using I / O Function of Microprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 어드레스 확장 회로도1 is an address expansion circuit diagram of the present invention.

Claims (2)

마이크로프로세서(1)와 마이크로프로세서 주변버퍼(2)와 메모리(8)로 구성되는 마이크로 프로세서 어드레스에 있어서, 상기 마이크로프로세서의 입출력 기능을 이용하여 상기 마이크로 프로세서 주변 버퍼(2)에 플립플롭(5-1-5-N)에 데이타를 기록하지 위한 디코우더(3)와 상기 디코우더에서 출력되는 신호(n-1)에 따라 상기 플립프롭으로 래치되는 데이타를 받아들여 메모리(8)의 어드레스 및 메모리 콘트롤 신호를 발생시켜주는 입력레지스터로 내장한 8비트 2진 카운터 (4-1-4-N)와 상기 디코우더의 출력 데이타를 내장하는 트리-스테이트 디 플립플록(5-1-5-N)과 상기 플립플롭과 카운터 제어 신호를 출력하는 카운터 및 플립플롭 제어회로(6)와 메모리(8)관리 시간을 적절하게 동작시키는 클럭(7)을 연결하여 어드레스를 확장시키고, 상기와 같이 연결된 구성에 메모리(8)를 연결구성하는 것을 특징으로 하는 마이크로 프로세서의 어드레스 확장법.In a microprocessor address composed of a microprocessor (1), a microprocessor peripheral buffer (2), and a memory (8), a flip-flop (5- 1-5-N) receives the data latched in the flip-flop in accordance with the decoder 3 for not writing data and the signal n-1 output from the decoder, and thus the address of the memory 8; And an 8-bit binary counter (4-1-4-N) built-in as an input register for generating a memory control signal, and a tree-state de-floplock (5-1-5) containing the output data of the decoder. -N), the counter and the flip-flop control circuit 6 for outputting the flip-flop and the counter control signal, and the clock 7 for properly operating the memory 8 management time are connected to extend the address, as described above. In the connected configuration Address extension method of the microprocessor, characterized in that the connecting configuration memory (8). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900013695A 1990-08-31 1990-08-31 Address-extended circuit KR940009821B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900013695A KR940009821B1 (en) 1990-08-31 1990-08-31 Address-extended circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013695A KR940009821B1 (en) 1990-08-31 1990-08-31 Address-extended circuit

Publications (2)

Publication Number Publication Date
KR920004978A true KR920004978A (en) 1992-03-28
KR940009821B1 KR940009821B1 (en) 1994-10-17

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ID=19303047

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900013695A KR940009821B1 (en) 1990-08-31 1990-08-31 Address-extended circuit

Country Status (1)

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KR (1) KR940009821B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496856B1 (en) * 1999-05-20 2005-06-22 삼성전자주식회사 Data processing system for expanding address

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452262B (en) * 2008-12-24 2011-07-13 中兴通讯股份有限公司 Output expanding method based on counter , apparatus and use system thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496856B1 (en) * 1999-05-20 2005-06-22 삼성전자주식회사 Data processing system for expanding address

Also Published As

Publication number Publication date
KR940009821B1 (en) 1994-10-17

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