KR960036677A - Control method and circuit of 8-bit static-ram card - Google Patents
Control method and circuit of 8-bit static-ram card Download PDFInfo
- Publication number
- KR960036677A KR960036677A KR1019950005263A KR19950005263A KR960036677A KR 960036677 A KR960036677 A KR 960036677A KR 1019950005263 A KR1019950005263 A KR 1019950005263A KR 19950005263 A KR19950005263 A KR 19950005263A KR 960036677 A KR960036677 A KR 960036677A
- Authority
- KR
- South Korea
- Prior art keywords
- ram card
- signal
- significant bit
- bit
- static
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
- H04N5/772—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera the recording apparatus and the television camera being placed in the same enclosure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/22—Employing cache memory using specific memory technology
- G06F2212/221—Static RAM
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Television Signal Processing For Recording (AREA)
- Static Random-Access Memory (AREA)
Abstract
본 발명은 8비트용 스테이틱-램 카드를 제어하는 방법 및 회로에 관한 것으로서, 제어신호에 의하여 지정된 주소를 지정하는 카운터; 상기 카운터의 출력 중에서 최하위비트 신호를 반전시키는 인버터; 그리고 상기 최하위비트의 반전된 신호와 반전되지 않은 신호를 읽기/쓰기 모드에 따라 선택적으로 출력하는 멀티플렉서; 를 포함한 것을 특징으로 하여, 현존하는 8비트용 스테이틱-램 카드의 대부분이 갖고 있는 구조적 문제점 즉, 읽기 모드(Read mode)에서 데이터의 짝수 바이트(even byte)와 홀수 바이트(odd byte)가 뒤바뀌어 출력되는 현상을 효율적으로 개선하여, 정확도가 높은 영상을 재현할 수 있다.The present invention relates to a method and circuit for controlling an 8-bit static-ram card, comprising: a counter for designating an address designated by a control signal; An inverter for inverting the least significant bit signal among the outputs of the counter; And a multiplexer for selectively outputting the least significant bit inverted signal and the uninverted signal according to a read / write mode. Structural problems of most existing 8-bit static RAM cards, that is, even and odd bytes of data in read mode. It is possible to effectively improve the phenomenon that is output by changing, and to reproduce an image with high accuracy.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 따라 8비트용 스테이틱-램 카드를 제어하는 블럭의 회로도이다.2 is a circuit diagram of a block for controlling a 8-bit static-ram card according to the present invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950005263A KR0165492B1 (en) | 1995-03-14 | 1995-03-14 | Method and circuit for controlling static ram card for 8-bit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950005263A KR0165492B1 (en) | 1995-03-14 | 1995-03-14 | Method and circuit for controlling static ram card for 8-bit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960036677A true KR960036677A (en) | 1996-10-28 |
KR0165492B1 KR0165492B1 (en) | 1999-03-20 |
Family
ID=19409779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950005263A KR0165492B1 (en) | 1995-03-14 | 1995-03-14 | Method and circuit for controlling static ram card for 8-bit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0165492B1 (en) |
-
1995
- 1995-03-14 KR KR1019950005263A patent/KR0165492B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0165492B1 (en) | 1999-03-20 |
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Legal Events
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110830 Year of fee payment: 14 |
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LAPS | Lapse due to unpaid annual fee |