KR950013255A - Address generator according to frame and field structure - Google Patents

Address generator according to frame and field structure Download PDF

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Publication number
KR950013255A
KR950013255A KR1019930021305A KR930021305A KR950013255A KR 950013255 A KR950013255 A KR 950013255A KR 1019930021305 A KR1019930021305 A KR 1019930021305A KR 930021305 A KR930021305 A KR 930021305A KR 950013255 A KR950013255 A KR 950013255A
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KR
South Korea
Prior art keywords
frame
address generator
field structure
generating
image data
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Application number
KR1019930021305A
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Korean (ko)
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KR960011738B1 (en
Inventor
신헌기
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배순훈
대우전자 주식회사
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Priority to KR1019930021305A priority Critical patent/KR960011738B1/en
Publication of KR950013255A publication Critical patent/KR950013255A/en
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Publication of KR960011738B1 publication Critical patent/KR960011738B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명에 의한 프레임 및 필드 구조에서의 어드레스 발생 장치는 헤더처리부(10)로부터 출력되는 선택신호를 이용하여 프레임 구조 또는 필드 구조에 따른 어드레스 발생신호를 변화시켜서 해당하는 어드레스를 발생시킴으로써 별도의 디코더가 필요없는 잇점이 있다.The address generator of the frame and field structure according to the present invention uses a selection signal output from the header processing unit 10 to change the address generation signal according to the frame structure or the field structure to generate a corresponding address, thereby providing a separate decoder. There is an advantage that is not necessary.

Description

프레임 및 필드 구조에 따른 어드레스 발생장치Address generator according to frame and field structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 어드레스 발생 블럭을 나타낸 도면이다.1 is a diagram illustrating a general address generation block.

제2도는 1프레임의 구조를 나타낸 도면이다,2 is a view showing the structure of one frame,

제3도는 본 발명에 의한 프레임 및 필드 구조에 따른 어드레스 발생장치를 나타낸 장치도이다.3 is a device diagram showing an address generator according to the frame and field structure according to the present invention.

제4도는 제3도에 있어서, 기입어드레스발생부를 상세히 나타낸 도명이다.4 is a diagram showing in detail the write address generation unit in FIG.

Claims (4)

프레임 구조 또는 필드 구조에 상관없이 화상데이타를 메모리에 기입 또는 독출하기 위한 어드레스를 발생하기 위한 프레임 및 필드 구조에 따른 어드레스 발생장치에 있어서, 방송시스템에 따른 화상데이타의 구조에 대한 정보로부터 선택 신호를 발생하기 위한 헤더처리부(10)와; 상기 헤더처리부(10)로부터 출력되는 선택신호에 따라서 상기 화상데이타를 상기 메모리에 기입하기 위하여 상기 구조에 해당하는 기입어드레스를 발생하기 위한 기입어드레스발생부(100)와; 상기 기입어드레스발생부(100)의 출력신호와 움직임 보정신호를 가산함으로써 상기 메모리로부터 상기 화상데이타를 독출시 상기 구조에 해당하는 독출어드레스를 발생하기 위한 독출어드레스발생부(200)를 포함함을 특징으로 하는 프레임 및 필드 구조에 따른 어드레스 발생장치.An address generator according to a frame and field structure for generating an address for writing or reading image data into a memory regardless of a frame structure or a field structure, wherein the selection signal is selected from information on the structure of the image data according to the broadcasting system. A header processing unit 10 for generating; A write address generation unit (100) for generating a write address corresponding to the structure in order to write the image data into the memory in accordance with the selection signal output from the header processing unit (10); And a read address generator 200 for generating a read address corresponding to the structure when reading the image data from the memory by adding the output signal and the motion correction signal of the write address generator 100 to each other. An address generator according to a frame and field structure. 제1항에 있어서, 상기 헤더처리부(10)는 상기 화상데이타의 구조가 프레임 구조인 경우, ‘로우’논리레벨상태를 출력하고, 필드 구조인 경우 인 경우 ‘하이’논리레벨상태를 출력함을 특징으로 하는 프레임 및 필드 구조에 따른 어드레스 발생장치.The method of claim 1, wherein the header processing unit 10 outputs a 'low' logic level state when the image data structure is a frame structure, and outputs a 'high' logic level state when the image data structure is a field structure. An address generator according to a frame and field structure, characterized in that. 제1항에 있어서, 상기 기입어드레스발생수단은 기입 및 독출 어그레스를 생성하는데 필요한 비트를 카운트하기 위한 카운터(20); 캐리신호를 발생시키기 위한 캐리신호발생부(30); 상기 카운터(20)로부터 출력되는 카운터값들과 상기 캐리신호발생부(30)로부터 출력되는 캐리신호에 대하여 상기 헤더처리부(10)로부터 출력되는 선택신호에 따라서 선택적으로 출력하기 위한 멀티플렉서(40)로 구성됨을 특징으로 하는 프레임 및 필드 구조에 따른 어드레스 발생장치.2. The apparatus of claim 1, wherein the write address generating means comprises: a counter (20) for counting bits necessary for generating write and read addresses; A carry signal generator 30 for generating a carry signal; A multiplexer 40 for selectively outputting counter values output from the counter 20 and a carry signal output from the carry signal generator 30 according to a selection signal output from the header processor 10. Address generator according to the frame and field structure, characterized in that configured. 제3항에 있어서, 상기 기입어드레스발생부(100)는 프레임 구조 또는 필드 구조에 따라서 소정의 카운트값뒤에 선택되어져야 할 카운트값을 선택하도록 제어하기 위한 복수개의 쓰리 스테이트 버퍼와 인버터를 더 포함함을 특징으로 하는 프레임 및 필드 구조에 따른 어드레스 발생장치.The apparatus of claim 3, wherein the write address generator 100 further includes a plurality of three state buffers and an inverter for controlling to select a count value to be selected after a predetermined count value according to a frame structure or a field structure. Address generator according to the frame and field structure, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930021305A 1993-10-14 1993-10-14 Adrs generator in frame & field structure KR960011738B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930021305A KR960011738B1 (en) 1993-10-14 1993-10-14 Adrs generator in frame & field structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021305A KR960011738B1 (en) 1993-10-14 1993-10-14 Adrs generator in frame & field structure

Publications (2)

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KR950013255A true KR950013255A (en) 1995-05-17
KR960011738B1 KR960011738B1 (en) 1996-08-30

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