KR960011738B1 - Adrs generator in frame & field structure - Google Patents

Abstract

The device for generating address of each data selectively in frame and field structure for HDTV, includes a header processing part including image data information and generating discriminating signal between frame and field structure data from input data, a writing address generation part with a 19-bit counter allotting writing selection address, a carry signal generator discriminating between odd number field and even number field for field structure, a multiplexer selecting between the counter and the carry signal generator, a selection address part providing memory with needed selection address signal by adder. The device simplifies the system and protects the system from image attenuation regardless of data format.

Description

Address generator according to frame and field structure

1 is a block diagram of a general address generator.

2 is a diagram illustrating a memory map structure of one frame.

3 is a block diagram of an address generator according to a frame and field structure according to a preferred embodiment of the present invention.

FIG. 4 is a detailed block diagram of the write address generator shown in FIG.

* Explanation of symbols for main parts of the drawings

10: header processing unit 20: counter

30: carry signal generator 40: multiplexer

50: adder 100: write address generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to HDTV (High Definition Television), and more particularly, to an address generator according to a frame and field structure suitable for selectively generating an address corresponding to each data structure in data processing of a frame structure and a field structure.

1 shows a block diagram of a conventional address generator.

Referring to FIG. 1, the AWP generation unit 1 is for generating a pixel write address from the start signal, and the ARM generation unit 2 outputs the output signal of the variable length controller and the output signal of the AWP generation unit 1. The motion correction read address is generated from the added signal, and the ARD generator 3 is used to generate the display data read address from the display control circuit.

FIG. 2 is a diagram showing a typical one-frame memory map structure. As shown in the same figure, one block is composed of 8x8 pixels, and one macroblock (MB) is composed of eight blocks. Slice is composed of 44 macroblocks, and one frame is composed of 60 slices.

In general, as shown in FIG. 2, in a frame structure of an HDTV, a picture sequence structure is divided into a frame structure and a field structure. In the frame structure, two fields (odd and even) belonging to one frame are regarded as one picture, and a GOP (Group Of Picture) is configured and encoded in units of frames.

On the other hand, in the field structure, one picture is composed of two fields (odd and even), but the two fields are completely independent encoded. Accordingly, the following even field can be predicted by using the odd field in the same picture. In other words, the GOP is configured in units of frames and encoded in units of fields.

Therefore, conventionally, as an example, as shown in FIG. 1, an address generator is separately provided to generate a corresponding address when the input data is a frame structure and a corresponding address when the input data is a field structure. . As a result, the conventional apparatus has to provide two address generators for the frame structure and the field structure separately or add a decoder, which not only complicates hardware but also increases the manufacturing cost of the entire system. In addition, when the frame structure of the broadcasting stations, i.e., the data formats are different, accurate picture reproduction is difficult, resulting in deterioration of image quality.

Accordingly, an object of the present invention is to solve the above-described problems of the prior art. In the data processing of the frame structure and the field structure, an address corresponding to each data structure is selectively generated by using a selection signal to generate an address. The present invention provides an address generator in accordance with a frame and field structure for unifying the hardware used.

In order to achieve the above object, the present invention provides an apparatus for generating a write address for writing image data having a frame data structure or a field data structure into a memory or a read address for reading image data written in the memory, A header processing unit for generating a selection signal corresponding to the data structure determination of the input bit stream based on the header information included in the input bit stream image data; When the input image data is written to the memory, a plurality of preset write addresses for respective unit pixels in horizontal and vertical directions corresponding to the frame data structure or the field data structure, respectively, in response to the generated selection signal. A write address generator for generating respectively; And when the image data written in the memory is read out, by adding a plurality of write addresses and motion correction signals for each of the generated unit pixels provided from the write address generator, to the frame data structure or the field data structure, respectively. An address generator according to a frame and field structure including a read address generator for generating a plurality of preset read addresses for respective unit pixels in a corresponding horizontal or vertical direction is provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an address generator according to a frame and field structure according to a preferred embodiment of the present invention. As shown in the figure, the address generator of the present invention includes a header processor 10, a write address generator 100, and a read address generator 200.

Referring to FIG. 3, the header processing unit 10 has information on the structure of image data according to a broadcasting system, and whether the input data is frame structure data or field structure data according to the header information included in the input bit stream. As a discrimination signal, a low or high level select signal is generated and provided to the multiplexer 40 in the write address generator 100 described later.

On the other hand, the write address generation unit 100 includes a counter 20 that counts 19 bits for allocation of the write read address A0-A18, and a carry signal for distinguishing the odd field and the even field when the input image data has a field structure. And a multiplexer 40 for selectively outputting the outputs of the counter 20 and the carry signal generator 30 based on the selection signal from the header processor 10. A write address required for storing input image data is generated in the omitted memory, and a write address for storing frame structure data or a write address for storing field structure data in response to the selection signal from the header processing unit 1 described above. Generate an address. A detailed write or read address generation process in the write address generator 100 will be described later in detail with reference to the accompanying FIG. 4 showing the detailed block configuration thereof.

On the other hand, the read address generator 200 adds the motion correction signal MV and the output signal of the multiplexer 40 in the write address generator 100 as shown in FIG. 50. The output of the adder 50 is provided to the memory as a read address signal A0-A18 which is required when reading image data stored in a memory (not shown).

FIG. 4 shows a detailed block diagram of the write address generator 100 shown in FIG.

First, before explaining the operation of FIG. 4, the reason why the 19-bit address A0-A18 is required for writing or reading data in the frame data structure or the field data structure is as follows.

That is, in the generation of the write and read addresses, assuming that the pixel data is written or read out by 4 pixels, one block of 8x8 pixels is written or read into the memory in units of 4 pixels so that one block is used. The address of requires 1 bit (0 or 1) (A0), and also requires access to 8 pixel lines in the vertical direction, so the vertical address requires 3 bits (A1-A3).

In addition, as shown in FIG. 2, for one macroblock MB including eight blocks, three blocks (two bits in the horizontal direction and one bit in the vertical direction) because they are four blocks in the horizontal direction and two blocks in the vertical direction. A write or read address is required (A4-A6).

Finally, for each frame, one slice of 44 macroblocks in the horizontal direction requires 6-bit write or read addresses (A7-A12). Also, in the vertical direction, one frame is 60 slices. A write or read address is required (A13-A18).

Therefore, assuming that the pixel data is written or read out by four pixels, in the case of a frame data structure (non-interlacing method), 0-3rd pixels are sequentially written (or read out) to one block for one block. And then write (or read from) the 4-7th pixel, and then write (or read from) the 8-11th pixel, and then process it. Moves to the next adjacent block. In other words, in the frame data structure, an address is generated such that the base block is written or read out in an odd, even alternating manner.

That is, the address generation signal for writing or reading in the case of the frame data structure is

Horizontal address (YH): A0, A4, A5, A7-A12

Vertical address (YV): A1-A3, A6, A13-A18

Become.

On the other hand, assuming that the pixel data is written or read out by four pixels, in the case of the field data structure (interlacing method), the 0-3rd pixel is written (or read) for one block, and then 4-7. After writing (or reading) the first pixel, one block is written to (or read from) the memory by skipping one line and writing (or reading) the 16-19th pixel, and then moving to the next block. Write (or read) the radix field. Then, one block is sequential by writing (or reading) the 8-11th pixel, then writing the 12-15th pixel, then skipping the first line, and writing (or reading) the 24-27th pixel. After writing to the memory (reading from the memory), it moves to the next block and writes (or reads) the even field. In other words, in the field data structure, an address is generated so that the pixel data of the odd field is written to the basic block once and then the pixel data of the even field is written or read out in the same order as the writing.

In this case, the memory map is not used separately, but the same memory map is used. However, by using the addresses different from each other, an address for motion compensation can be more easily generated.

Therefore, the address generation signal for writing or reading in the case of the field data structure is

Horizontal address (YH): A0, A4, A5, A7-A12

Vertical address (YV): Ca, A1, A2, A6, A13-A18

Become.

Here, as an example, in the case of an image system in which one frame constitutes 1/30 second, the carry signal Ca for field division is to repeat a logic state of high or low level every 1/60 (ie, , 1 in the radix field, 0 in the even field. That is, the timing of the carry signal Ca output from the carry signal generator 30 of FIG. 3 may be repeated at a logic level of high or low level at intervals of 1/60.

As can be seen from the above, in the address generating apparatus according to the present invention, in the frame structure or the field structure, the horizontal address generating signal is the same and the vertical address generating signal is different from each other.

Next, a process of generating a corresponding write or read address when the input bit stream is a frame data structure or a field data structure according to the present invention will be described in detail with reference to FIGS. 3 and 4.

Referring to FIG. 3, the write address generator 100 includes a counter 20, a carry signal generator 30, and a multiplexer 40. In FIG. 4, a counter is provided for convenience of explanation and improvement of understanding. 20 and the carry signal generator 30 are omitted, and only their output signals are shown.

Referring to FIG. 4, the first and second three state buffers 11 and 13 and the inverter 12 have an address to be counted after the address generation signal A2 in the frame data structure or the field data structure. This function is to select generation signal A3 or A4.

On the other hand, in Fig. 3, since the header processing section 1 has information on the structure of the image data according to the broadcasting system, the header processing section 1 generates a selection signal based on the header information included in the input bit stream and sends it to the multiplexer 40. Is authorized. For example, when the configuration of the image data is a frame structure, a selection signal in a "low" logic state is output, and in the case of a field structure, a selection signal in a "high" logic state is output.

In addition, the counter 20 is configured as a 19-bit counter, and outputs a counter value from A0 to A18 to the multiplexer 40 together with the carry signal Ca output from the carry signal generator 30. More specifically, the counter 20 outputs the address generation signals A0-A3 to the multiplexer 40 and provides the address generation signals A4-A18 directly to the output of the multiplexer 40, as can be seen from FIG. do. At this time, A0, A4, A5, A7 to A12 of the counter values output from the counter 20 correspond to the horizontal address generation signal YH, and A1-A3, A6 and A13-A18 of the counter values are vertical address generation signals. Corresponds to (YV).

In the present invention, in order to implement the AWP generator 1 and the ARM generator 2 in the prior art shown in FIG. It was designed as shown in Table 1.

That is, when the selection signal output from the header processing unit 10 is in a 'low' logic state, since the configuration of the image data is a frame structure, the multiplexer 40 outputs the counter 20 to the input signal Ca, A1. , A2, A3 Select A1, A2, A3 among the counter values and output to AV0, AV1, AV2. At this time, A6 and A7 to A12 of the counter values output from the counter 20 are output to AV3 and AV4 to AV9.

For example, in the frame structure, the vertical address value is 8,8 blocks in 0,1,2,3,4,5,6,7 → 0,1,2,3,4,5,6,7 for one frame. →… → should occur as 0,1,2,3,4,5,6,7 To this end, the input / output relationship of the multiplexer 40 is shown in the table below.

On the other hand, when the selection signal output from the header processing unit 10 is a 'high' logic state, since the configuration of the image data is a field structure, the multiplexer 40 is output from the counter 20 and is applied as an input signal. Selects Ca, A1, and A2 among the A2 and A3 counter values and outputs them to AV0, AV1, and AV2. At this time, among the count values output from the counter 20, A6 and A7 to A12 are output to AV3 and AV4 to AV9 as in the above-described frame structure.

For example, in the field structure, the vertical address value is 8, 8 blocks, 0, 2, 4, 6 → 0, 2, 4, 6 → ... → 0, 2, 4, 6 → 1, 3 for one frame. , 5,7 → 1,3,5,7 → ... → 1,3,5,7 Where 0, 2, 4, and 6 are vertical addresses in the odd field, and 1, 3, 5, and 7 are vertical addresses in the even field. For this purpose, the input / output relationship of the multiplexer 40 is shown in a table as shown in Table 3a for the odd field and Table 3b for the even field.

Therefore, in the frame data structure, since the signal applied to the control terminal of the first tri-state buffer 11 is 'low', the buffer 11 is turned off and is applied to the control terminal of the second tri-state buffer 13. Since the signal is 'high', the buffer 13 is turned on so that the address generation signal to be counted after A2 becomes A3.

On the other hand, in the field data structure, since the signal applied to the control terminal of the first tri-state buffer 11 is 'high', the buffer 11 is turned on and is applied to the control terminal of the second tri-state buffer 13. Since the signal is 'low', the buffer 13 is turned off and the address generation signal to be counted after A2 is selected as A4.

Therefore, as can be seen from the above, in the address generator in the frame and field structure according to the present invention, the address generation signal in accordance with the frame structure or the field structure is changed by using the selection signal outputted from the head processor. By generating the address, the configuration of the entire system can be simplified since there is no need to separately provide two address generators or add a decoder as in the conventional apparatus described above.

In addition, even if the frame structure is different between broadcast stations, information (header information) about the bit stream is added to the bit stream, and the head processor detects it and outputs a corresponding selection signal so that an appropriate address is required for addressing the memory. In this case, accurate picture reproduction is possible even if the data formats are different between broadcast stations, and thus, the softening of the picture quality caused by the data format between the broadcast stations in the conventional apparatus can be prevented.

Claims (4)

An apparatus for generating a write address for writing picture data having a frame data structure or a field data structure into a memory or a read address for reading picture data written to the memory, the device being included in an input bit stream type picture data. A header processor (10) for generating a selection signal corresponding to the data structure determination of the input bit stream based on the received header information; When the input image data is written to the memory, a plurality of preset write addresses for respective unit pixels in horizontal and vertical directions corresponding to the frame data structure or the field data structure, respectively, in response to the generated selection signal. A write address generator 100 for generating respectively; And when the image data written in the memory is read out, by adding a plurality of write addresses and motion correction signals for each of the generated unit pixels provided from the write address generator 100, thereby generating the frame data structure or field data. An address generator according to a frame and field structure comprising a read address generator (200) for generating a plurality of preset read addresses for respective unit pixels in a horizontal or vertical direction respectively corresponding to the structure. The method of claim 1, wherein the header processing unit 10 generates a logic signal having a 'low' level as the selection signal when the input image data structure is a frame structure, and generates a high signal as the selection signal when the field structure is a frame structure. An address generator in accordance with a frame and field structure, characterized by generating a logic signal of a level. The apparatus of claim 1, wherein the write address generator (100) comprises: In response to the generated selection signal, a count value necessary for allocating an upper write address among the vertical write addresses used to write the image data into the memory is generated, and the lower write address and the horizontal write address among the vertical write addresses are generated. Generating a plurality of count values corresponding to the data structure of the image data required to generate a plurality of predetermined read addresses for each unit pixel in the horizontal and vertical directions for reading the image data written into the memory. Counter 20; A carry signal generator 30 for generating a carry signal for distinguishing an odd field and an even field when the image data has a field data structure; And a plurality of higher write addresses for respective unit pixels in the vertical direction corresponding to the frame data structure according to the count value from the counter 20 in response to the generated selection signal when the image data is a frame data structure. When the image data is a field data structure, each unit pixel in the vertical direction corresponding to the field data structure according to the counter value from the counter 20 is generated in response to the generated selection signal and the carry signal. And a multiplexer 40 for selectively outputting a plurality of upper write addresses for the plurality of upper and lower write addresses, wherein the plurality of upper write addresses among the vertical write addresses from the multiplexer 40, the plurality of lower write addresses from the counter 20, and Finally outputting a horizontal write address from the counter as the predetermined plurality of addresses The address generator in accordance with the frame and the field structure, characterized in that the. 4. The method of claim 3, wherein when the frame data structure and the field data structure are each composed of 8x8 blocks, macroblocks, and slice data, the plurality of upper write addresses are arranged in a plurality of horizontal and And a plurality of lower write addresses are a plurality of horizontal and vertical addresses for the macroblocks and slices.