KR970008414B1 - Circuti for compensating motion of half - pixel in motion picture decoding apparatus of parallel - transacting structure - Google Patents

Abstract

A half pixel motion compensation circuit of a motion image decoder is disclosed. The circuit comprises a first latch(41) for controlling a data transmission so as to detect an average value of a predetermined unit of data read at a memory(30); a horizontal motion detector(42) for calculating the horizontal average to detect a horizontal motion in case of a half-pixel motion compensation; and a vertical motion detector(44) for detecting a vertical motion to provide a data which can be processed by a differential code modulation.

Description

Half-Pixel Motion Compensation Circuit in Video Decoding Device with Parallel Processing Structure

Figure 1 is a brief description showing an embodiment of a video decoding apparatus having a conventional half-pixel motion compensation function

FIG. 2 is a block diagram showing an embodiment of the half-pixel motion compensator shown in FIG.

FIG. 3 is a detailed block diagram of the second latch shown in FIG. 2, which shows an embodiment of a half-pixel motion compensation circuit in a video decoding apparatus of a parallel processing structure according to the present invention.

* Explanation of symbols for main parts of the drawings

41, 43: first and second latch 42: horizontal movement detection means

44: vertical movement detection means 431,433: third and fourth selection means

432: latch means 4321, 4222, 4223, 4324: third to sixth latches

The present invention relates to a half-pixel motion compensation circuit in a video decoding apparatus having a parallel processing structure. In particular, the present invention relates to a half pixel moving compensation in a video decoding apparatus having a parallel processing structure in which a screen is divided into a predetermined size and processed in parallel. It is about a circuit.

In general, high-definition video signal processing systems such as HDTV (high definition television) require high-speed signal processing to transmit large amounts of data. In order to accomplish this, a commonly used method is to configure a system having the same structure in parallel and process the above-mentioned data simultaneously. When using such a method, circuits necessary for processing the data (for example, motion compensation Can be operated at a lower speed in proportion to the number of divided screens.

FIG. 1 is a block diagram showing an embodiment of a video decoding apparatus having a conventional half-pixel motion compensation function. In particular, FIG.

First, DM (Module Data) applied to the data rearrangement unit 10, that is, DM0, DM1, DM2, and DM4, are digital data applied in a bitstream form, and are image data divided into four screens. That is, DM0 is the screen data of the first module (module 1), DM1 is the screen data of the second module (module 2), DM2 is the screen data of the third module (module 3), and DM3 is the third module ( The screen data of the module 3), and DM3 is the screen data of the fourth module (module 4). At this time, such DM0, DM1, DM2, DM4 is applied simultaneously to the data rearrangement unit (10).

Accordingly, the data rearrangement unit 10 directly outputs the data corresponding to the first of each screen in the order of Module 1, Module 2, Module 3, and Module 4 for each screen data simultaneously applied as described above. The data applied next is also rearranged so that the data is output serially in the above-described module order.

The rearranged data is output to the differential phils code modulator 20, and the differential phils code modulator 20 is output from the data and the data reordering unit 10 in the order described above by the data rearrangement unit 10. FIG. The half-pixel motion compensated value is output by performing differential difference code modulation in order corresponding to the data, and the output data is applied to the memory 30.

Thus, the memory 30 stores data in a memory area allocated to each divided screen. The data stored in the memory 30 reads the data stored by the motion vector output from the variable length decoder not shown and outputs the data to the anti-pixel motion compensator 40 and the display not shown.

Next, the half pixel motion compensator 40 compensates for the movement of the data read from the memory 30, and compensates for the movement of the half pixel data considering the details and the transfer amount compared to the single pixel. In the compensation method of the half-pixel motion compensator 40, since half-pixel positions are located at the centers between single pixels, the average of single pixel data values located near the horizontal and vertical sides with respect to the half-pixel positions to be compensated Is done by taking.

A half pixel motion compensator 40 will be described in more detail with reference to FIG. 2.

FIG. 2 is a detailed block diagram of the half pixel motion compensation circuit 40 shown in FIG. 2 illustrates an example in which the processing unit is 8 pixel data.

First, when the data output from the memory 30 is output in units of 8 pixels, the 9 pixel data including the predetermined 1 pixel data adjacent through the internal data rearrangement circuit (not shown) is arranged to form one processing unit. When applied to the first latch 41, the first latch 41 is processed to enable horizontal average detection of the applied data and outputted to the horizontal movement detecting means 42.

Next, the horizontal movement detecting means 42 detects the horizontal movement of the corresponding 8 pixel data by using the data output from the first latch 41. That is, the 9 pixel data output from the first latch 41 is applied to the horizontal average detector 422 as it is to detect the average in the horizontal direction, and the horizontal delay detection is not necessary with the first delay unit 422. Only 8 pixels of data are applied. At this time, the horizontal average detector 421 detects an average of pixels adjacent to the horizontal side with respect to the applied 9 pixel data, and outputs eight average values, and the first delay unit 422 is performed in the horizontal average detector 421. Delayed 8-pixel data applied during the output.

The first selecting means 423 selects a signal output from the horizontal average detector 421 when performing half pixel motion compensation, and a signal output from the first delay unit 422 when performing single pixel motion compensation. Select to print. At this time, the selection control is determined according to the position of the motion vector.

In addition, the data output from the first selecting means 423 is applied to the second latch 43 in the form of a data value of eight pixels. The second latch 43 stores 8 pixel data values previously applied to enable vertical average detection of data applied in units of 8 pixels, and outputs the 8 pixel data values currently applied to the vertical movement detecting means 44. It works.

Accordingly, the vertical motion detecting means 44 applies 16 pixel data applied by the operation of the second latch 43 to the vertical average detector 441, and the 8 pixel data currently applied is applied to the second delay unit 442. To be applied).

Accordingly, the vertical average detector 441 detects the vertical average value between the previous 8 pixel data and the current 8 pixel data with respect to the applied 16 pixel data, and outputs 8 average values, and the second delay unit 442 outputs the second average value. The current 8-pixel data value output from the latch 43 is delayed and output by the time processed by the vertical average detector 441.

Next, the second selection means 443 selectively outputs the signals output from the vertical average detector 441 and the second delay unit 442 as in the first selection means 423 described above. At this time, the output data is output to the differential pulse code modulator 20.

However, such a half-pixel motion compensator 40 has no problem when processing a single screen, but when a plurality of screens are divided and processed in parallel, a problem occurs in detecting an average value in the vertical direction. That is, the second latch 43 stores and processes the data currently processed for the next line. In the case of parallel processing, the data input to the anti-pixel motion compensator 40 is data of another module. (As described above, since the same sequence of 8 pixel data is sequentially applied per divided screen, for example, if the previously applied data is DM0, the corresponding 8 pixel data is DM1.) Vertical average detection 16 pixels output from the second latch 43 become 8 pixel data of previously stored DM0 and 8 pixel data of the currently applied DM1, and are perpendicular between the data of the own module and the previous module during vertical average detection. Since the average is detected, there is a problem that a desired vertical average value cannot be obtained.

Accordingly, an object of the present invention is to provide a half pixel motion compensation circuit in a video decoding apparatus having a parallel processing structure for detecting an accurate vertical mean when compensating for half pixel movement in a parallel decoding structure.

In order to achieve the above object, the present invention provides a half pixel movement compensation for data read from a memory storing previous frame data which has been compensated for motion, and outputs the data to be differentially coded with the data applied as the current frame data. A half-pixel motion compensation circuit for compensating motion of a divided screen of a video decoding apparatus having a pixel motion compensator, wherein the data transfer is controlled to detect a horizontal average with respect to data of a first predetermined unit read from a memory. A first latch for; Horizontal motion detection means for detecting horizontal motion by calculating a horizontal average when performing half pixel motion compensation on the pixel data of the first predetermined unit provided in the first latch; A second latch for performing separate transmission processing for each screen divided to enable vertical motion detection with data in its own module with respect to data output from the horizontal motion detecting means; And vertical movement detection means for detecting the vertical movement by the data output from the second latch and outputting the data to perform differential pulse code modulation.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

FIG. 3 is a detailed block diagram of the second latch 43 used in the anti-pixel motion compensator 40 shown in FIG. 2, and shows the anti-pixel motion compensation circuit in the video decoding apparatus of the parallel processing structure according to the present invention. A block diagram illustrating one embodiment. In this case, the remaining parts that are the same as those of FIG. 2 are omitted.

That is, FIG. 3 is an embodiment implemented according to the present invention with respect to the second latch 43 of FIG. 2, and latch means 432 for allocating a latch per divided screen to transmit data for each divided screen number. And third selecting means 431 for selecting a corresponding output terminal for the input signal so that the 8 pixel data value output from the first selecting means 423 is transferred to the corresponding latch, and outputting from the latch means 432. Fourth selecting means 433 respectively selects the data of the corresponding screen among the signals to be output to the vertical average detector 441 and the second delay unit 442 in the vertical motion detecting means 44.

In addition, the latch means 432 is composed of four latches when the screen is divided into four, that is, the third latch 4321 assigned to the module 1 screen of DM0 and the fourth screen assigned to the module 2 screen of DM1. A latch 4322, a fifth latch 4323 assigned to the module 3 screen of DM2, and a sixth latch 4324 assigned to the module 4 screen of DM3. At this time, the third selecting means 431 is composed of a demultiplexer, and the fourth selecting means 433 is composed of a multiplexer.

Hereinafter, the operation of the present invention will be described.

In the second latch 43 configured as shown in FIG. 3, when data of DM0 is first applied to data of 8 pixel units applied in the order of DM0, DM1, DM2, and DM3 by parallel processing, the second latch 43 is configured as shown in FIG. It is applied to the second latch 43, that is to the third selection means 431 via the latch 41 and the horizontal movement detecting means 42.

Accordingly, since the third selecting means 431 is configured as a demultiplexer, one input signal is output through one output terminal among a plurality of output terminals. Currently, since the data corresponding to the DM0 module is applied, the third input means 431 is applied. Output to 3 latches 4321.

Next, the third latch 4321 outputs the eight previously applied horizontal average values and the currently applied eight horizontal average values to the fourth selecting means 433, and the fourth selecting means 433 is configured for the current DM0 module. Since the selection control signal is applied according to the processing, the signal output from the third latch 4321 is selected and transferred to the vertical motion detecting means 44 to obtain a vertical average.

When data of the DM1 module corresponding to the next sequence is applied, the eight horizontal movement detection values are output through the same process as the above-described DM0 and transmitted to the fourth latch 4322 through the third selecting means 431. In addition, the fourth selecting means 433 is controlled to transmit the data output from the fourth latch 4322 to the vertical movement detecting means 44.

The same applies to DM2 and DM3, and only the fifth latch 4323 is selected in the case of DM2, and the sixth latch 4324 is selected in the case of DM3.

As described above, the present invention provides an anti-pixel motion compensation circuit suitable for a video decoding apparatus that is processed in parallel by screen division, thereby providing accurate motion compensation.

Claims (4)

Half-pixel motion compensator 40 for compensating half-pixel motion with respect to the data read from the memory 30 storing the previous frame data which has been compensated for motion, and outputting the difference pulse code with the data applied as the current frame data. An anti-pixel motion compensation circuit for compensating for motion of a divided screen of a video decoding apparatus having a; A first latch (41) for controlling data transmission to detect a horizontal average with respect to data of the first predetermined unit read from the memory (30); Horizontal movement detection means (42) for detecting horizontal movement by calculating a horizontal average when performing half pixel movement compensation on the pixel day of the first predetermined unit provided by the first latch (41); A second latch 43 for performing separate transmission processing for each screen divided so that vertical motion detection is possible with data in its own module with respect to the data output from the horizontal motion detecting means 42; And a vertical motion detecting means (44) for detecting the vertical motion by the data output from the second latch (43) and outputting the data as data capable of performing differential pulse code modulation. A half pixel motion compensation circuit in a video decoding apparatus. The second latch 43 is output from the latch means 432 made up of latches equal to the number of divided screens and the constant horizontal motion detecting means 42 to transmit data for each divided screen number. First selecting means 421 for selectively controlling an output end to transmit the data to the corresponding one of the latches, and output the data to the vertical movement detecting means 44 with respect to the data output from the latching means 432. And a second selection means (433) for selective control of the input end to enable the half-pixel motion compensation circuit in the video decoding apparatus of the parallel processing structure. 3. The half-pixel motion compensation circuit of claim 2, wherein the first selecting means (431) comprises a demultiplexer. 4. The half-pixel motion compensation circuit according to claim 2 or 3, wherein the second selecting means (433) comprises a multiplexer.