KR960006923Y1 - Circuit for generating address - Google Patents

Abstract

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Description

Pixel Write Address Generation Circuit

1 is a block diagram of the present invention

2 is a truth value display according to the operation of the present invention

* Explanation of symbols for main parts of the drawings

1: QP count 2: Count signal generator

3: MB counter 4, 5: buffer

The present invention relates to a pixel write address issue circuit, and more particularly, to a simple address generation circuit for recording a pixel in a memory device in a MPEG (Moving Picture Experts Group) method.

In general, a memory module having an MPEG structure stores data input from a variable length decoder in a frame memory, and reads the image data in the interlaced scanning order in units of preset pels. The control target memory is composed of a display frame memory and a motion compensation predictive memory combined memory block. The memory block is composed of two blocks, and writing and reading can be performed in units of frames. The memory block also consists of four memory cells, each cell consisting of a luminance (Y) cell and a color (C) cell.

Such memory blocks can be written / read by address and control signals. To date, memory modules include software means that rely on complex circuitry or clock generation circuitry to perform the aforementioned operations. Accordingly, there has been a need for a pixel write address generation circuit that can be more easily implemented and easily implemented in real time.

Accordingly, an object of the present invention is to provide a pixel write address generation circuit which can more easily implement the addressing of a macro block (MB) according to the block structure of MPEG, and can operate at a high speed.

In order to achieve the above object, the present invention provides a quantization parameter (QP) counter that receives a clock, a coefficient signal generator that receives the output of the quantization parameter (QP) counter and generates coefficient signals CO to C6, and A macroblock MB that receives the output of the counting signal generator at the clock stage and processes the macroblock MB, and outputs a slice processing end (EOSL) signal, and a luminance / color selection signal Y from the counting signal generator. And first and second buffers selectively operating in response to / C-SEL to output the count signals CO to C6 as addresses Do0 to Do6.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a pixel write address generation circuit according to the present invention, and the present invention as shown in the drawing includes a quantization parameter (QP) counter 1 that receives a clock and an output of the QP counter 1. Selects the luminance / color from the count signal generator 2, the macro block (MB) counter 3 receiving the output of the count signal generator 2 at the clock stage, and the count signal generator 2; A first buffer 4 for receiving the signal Y / C SEL and outputting an address signal and a second buffer 5 for inverting the luminance / color selection signal Y / C SEL and outputting the address signal; It is provided.

The present invention has to process 64 pixels, MB counter (3) which processes 10 blocks and 44 macroblocks (MB), EOSL which indicates that the slice is finished, and EOMB which indicates that macroblock has been processed. Signal and YC-SEL to select luminance (Y) and color (C) signals to select U or V signals, and addressable by considering 2: 1 decimation vertically according to Y and C. It is structured.

The present invention generates EOMB signals by processing 64 pixels and 10 blocks, and generates EOSL signals by processing 44 MB using the EOMB signals. In the circuit according to the present invention, since the color signal C is decimated with respect to the luminance Y at 4: 1 horizontal and 2: 1 vertical, this should be taken into account when addressing, which is described with the aforementioned YC-SEL signal. The choice was made.

In the figure, signal CO-C7 is for pixel address, signal MO-M5 is for macroblock MB address, and Y / C-SEL is a signal for selecting C or Y.

2 is a truth table according to the present invention and shows an address value according to the YC-SEL signal.

When the Y / C SEL signal is H, that is, when a color (C) signal address is required, the address data is 0, 1, C1, C2, 0, C0, C3, and the Y / C SEL signal is L. That is, when the luminance Y signal address is required, it can be seen that the above-described signals CO to C6 are supplied through the buffer 4 as the address data Do0 to Do6.

Therefore, the present invention configured as described above is a circuit for realizing MB addressing according to the structure of MPEG, and each component uses 74F series ICs to operate at high speed, and Y / C-SEL. Made the signal effective. Even in the vertical decimation relationship, the constant 1 is connected to the address terminal, and the circuit configuration is simple and useful.

Claims (1)

A quantization parameter (QP) counter (1) receiving a clock, A coefficient signal generator 2 which receives the output of the quantization parameter QP counter 1 and generates coefficient signals C0 to C7; A macroblock (MB) counter (3) that receives the output of the coefficient signal generator (2) as a clock stage to process a macroblock (MB), and outputs an EOSL signal when 44 macroblocks have been processed. It selectively operates in response to the luminance / color selection signal Y / C-SEL from the coefficient signal generator 2, so that the coefficient signals C0 to C7 from the signal generator 2 are address signals Do0. And first and second buffers (4, 5) for outputting to (Do6).