KR960012488B1 - Scan converter for digital video processor - Google Patents

Abstract

The device includes a clock output means for mixing horizontal synchronizing signal and vertical synchronizing signal and generating a clock signal, a delaying means(20) for delaying and generating the vertical synchronizing signal and a clock of clock output means during finite time, a recoding address output means(30) for generating an address signal continuously, a single address output means(40) for generating a single address signal, and selecting means(50) for generating the signal selectively.

Description

Scanning method switching device of digital image processing device

1 is a block diagram of a scanning method switching device of a conventional digital image processing apparatus.

2 is a block diagram of a scanning method switching device of a digital image processing apparatus according to the present invention.

3 is a main input / output state waveform diagram of a scanning method switching device of a digital image processing apparatus according to the present invention;

4 is an input / output state diagram of a scanning method switching device of a digital image processing apparatus according to the present invention.

5 is an input / output state diagram according to another embodiment of a scanning method switching device of a digital image processing apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: clock output circuit 20: delay circuit

30: write address output circuit 40: read address output circuit

50: selection circuit 60: storage circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus, and more particularly, to a scanning method switching device of a digital image processing apparatus for converting and outputting image data applied by a progressive scanning method into a sequential scanning method.

In general, the two-dimensional plane of the rectangular shape from the upper left to the right by drawing a line to fill at evenly spaced intervals of the typical image scanning method is a typical scanning method and a progressive scan method.

Sequential scanning (or also known as progressive scanning) is a scanning line from the top to the bottom of a picture or screen that is a two-dimensional plane when the picture is detected or an electrical video signal is displayed on the screen to output the picture as an electrical signal. It's a way to inject without skipping.

In contrast, a parallel scan scans one or more scan lines from the top to the bottom of the image or screen. NTSC (National Television System Committee) type television signal is an assault scan method. It scans two screens at 1/60 second intervals twice, giving the effect of changing 60 pictures per second.

However, in order to process a signal, a parallel scan type image signal needs to be changed to a forward scan type in a digital image processing apparatus. In this way, the conventional method for converting the progressive scan method into the forward scan method is conceptually described. Two frame memories (1), (2) and two switches (SW1) capable of storing image data corresponding to one frame are described. And (SW2).

That is, the image data applied in a parallel scan manner while the switch SW1 is switched to the terminal a is stored in the first frame memory 1, at which time the switch SW2 switches to the terminal b. The image data stored in the second frame memory 2 are output in a sequential scanning manner.

Thereafter, the switch SW1 is switched to the terminal b and the switching SW2 is switched to the terminal a so that the first frame memory 1 stores the image data stored in the progressive scan method in a sequential scanning manner. The second frame memory 2 stores image data which is applied in a parallel scan method.

By using two frame memories as described above, it is possible to easily convert the image data of the parallel scan type into the progressive scan type. However, since the memory for recording and outputting image data is required to have a large capacity and high speed, the price is usually high, so the production value is conventionally used using two frame memories capable of storing image data corresponding to one frame. There is a problem that this becomes expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to use a memory capable of storing image data corresponding to 3/4 frames to change the progressive scan type image data into a progressive scan type. The present invention provides a scanning method switching device of an image processing apparatus.

A feature of the present invention for achieving the above object is, in a digital image processing apparatus, a clock output circuit for combining a horizontal synchronous signal and a vertical synchronous signal and outputting them as a clock signal, a vertical synchronous signal and a clock of the clock output circuit. A delay circuit for delaying the output by a time corresponding to the number of lines-1 of one field and outputting the number of lines of one field + Sequentially stores the write address signals corresponding to and outputs the remaining write address signals two times in sequence after outputting the write address signals that sequentially designate one field line in synchronization with the clock of the clock output circuit according to the vertical synchronization signal. A write address output circuit; The same address signals as the write address output circuit are sequentially stored as read address signals, and n is synchronized with the clock of the delay circuit according to the vertical synchronization signal of the delay circuit. Until (n, + n) After sequentially outputting the read address signals corresponding to (n = 1, 2, 3…), n is Until a read address output circuit for sequentially outputting a read address signal corresponding to + n total number of lines in a field + n); A selection circuit for selectively outputting a write address signal and a read address signal of said write address output circuit and read address output circuit in accordance with a clock signal of said delay circuit; Total number of lines in one field + A line image stored in the input line image data at a address corresponding to a write address signal of the selection circuit according to the clock of the delay circuit, and a line image stored at the address corresponding to the read address signal of the selection circuit. A scanning method switching device of a digital image processing apparatus having a storage means for outputting data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a digital image processing apparatus according to the present invention. The clock output circuit 10, the delay circuit 20, the write address output circuit 30, the read address output circuit 40, and the selection circuit 50 are shown in FIG. , And the storage circuit 60.

More specifically, the clock output circuit 10 is a combination of an external reset signal, a horizontal and a vertical synchronization signal, and outputs a clock signal. In this embodiment, the clock output circuit 10 includes an AND gate A1. The delay circuit 20 is connected to the clock output circuit 10 so that the clock signal of the clock output circuit 10 is applied to the storage circuit 60. The total number of one field lines of image data is -1 lines. Delaying by the corresponding time to output to the terminal (a) while delaying the external vertical synchronizing signal by the total number of lines of one field -1 line to output to the terminal (b). In addition, the write address output circuit 30 has one field line number of image data applied to the storage circuit 60+. The write address signals corresponding to the storage signals are sequentially stored, and the write addresses for sequentially designating the lines of one field are sequentially output in synchronization with the clock of the clock output circuit 10 applied to the terminal clk. When the synchronization signal is applied to the terminal ch, it is configured to sequentially output the remaining write address signals in synchronization with a clock, and to sequentially output the remaining write address signals once again. The write address output circuit 30 is configured to reset to an initial state when an external reset signal is applied to the terminal clr.

The read address output circuit 40 connected to the delay circuit 20 is configured to include the same addresses as the read address signals 30 as the read address signals, and from the delay circuit 20 to the terminal ch. N is applied when the clock signal applied to the terminal clk is at a high level. Until (n, + n) outputs a read address signal corresponding to + n), and when the vertical synchronization signal is applied to terminal ch again, n Until A process of sequentially outputting read address signals corresponding to + n and the number of lines of one field + n) is sequentially performed.

The read address output circuit 40 is configured to be cleared when an external reset signal is applied to the terminal clr.

The selection circuit 50 connected to the write address output circuit 30, the read address output circuit 40, and the delay circuit 20 is connected to the write address output circuit 3 ² according to the clock signal of the delay circuit 20. And the multiplexers MUX1 and MUX2 for selectively applying the write and read address signals of the read address output circuit 40 to the storage circuit 60. In this case, the multiplexer MUX1 is configured to output the pixel clock applied to the terminal a when the clock signal applied to the terminal S1 is at a low level.

The multiplexer MUX2 outputs the read address of the read address output circuit 40 when the low level is applied from the multiplexer MUX1 to the terminal S2, and the multiplexer MUX2 outputs the read address of the read address output circuit 40 from the multiplexer MUX2. When the high level is applied, the write address of the write address output circuit 30 is output.

The storage circuit connected to the selection circuit 50 is for storing and outputting image data at a address corresponding to a read address signal and a write address signal applied from the selection circuit 50, and the memory 61 and the pixel. The clock output unit 62, the pixel address output unit 63, and the input / output state control unit 64 are provided.

In this case, the pixel clock output unit 62 oscillates and outputs a pixel clock of a predetermined period for controlling input and output of pixel data applied to the memory 61, and the pixel address output unit 63 is connected to the pixel clock. Synchronize to output the address of the pixels corresponding to one line. The pixel address output unit 63 inputs the clock signal of the clock output circuit 10 to the terminal clr to be cleared when the clock signal is at a high level.

The memory 61 is (number of lines of a field + Memory line address corresponding to the < RTI ID = 0.0 >),< / RTI > and the pixel address for specifying pixels constituting one line.

The memory 61 is driven when a high level clock signal is applied from the clock output circuit 10 to the terminal cs. The memory 61 is driven when a low level pixel clock is applied to the terminal R / W. ) Stores the pixel data input to the pixel address applied to the line address interrupter (b), and the line address applied to the terminal (a) when a high level pixel clock is applied to the terminal (R / W). The pixel data stored in the pixel address applied to the terminal b is output.

The input / output state controller 62 connected to the memory 61 controls the state in which the memory 61 inputs / outputs pixel data. When the pixel clock of the pixel clock output unit 62 is low level, the memory ( A buffer B1 for outputting read pixel data of 61 and a second buffer B2 for applying pixel data input to the memory 61 when the pixel clock of the pixel clock output unit 62 is at a high level.

As described above, the scanning method switching device of the digital image processing apparatus according to the present invention can convert the pixel data of the progressive scan method into the forward scanning method by using a memory for storing pixel data corresponding to 3/4 frames. do.

This process is described in detail below. First, in the present embodiment, it is assumed that a frame is composed of a total of eight lines, and one line is formed of 36 pixels. In this assumption, when the reset signal is in the low level as shown in FIG. 3, the write address output circuit 30, the read address output circuit 40, and the pixel address output section 63 will be cleared to the initial state. At this time, when the reset signal is in the high level state and the period of the vertical synchronization signal and the horizontal synchronization signal is in the high level state, the AND gate A1 outputs the recording address as the clock signal as the clock signal. It is applied to the circuit 30 and the delay circuit 40, respectively.

At this time, the write address output circuit 30 sequentially outputs the address of the memory 61 by using the horizontal synchronization signal of the AND gate A1 as a clock as the vertical synchronization signal is applied.

In the present embodiment, it is assumed that the line address of the memory 61 is composed of A, B, C, D, E, and F.

Under this assumption, the write address output circuit 30 first outputs addresses, A, B, and C. At this time, the delay circuit 20 outputs the output of the AND gate A1 and the vertical synchronization signal. Since it delays by -1, a low level signal is applied from the delay circuit 20 to the multiplexer MUX1 until the time point t1. That is, since the multiplexer MUX1 outputs a high level voltage Vcc while the write address output circuit 30 outputs the write addresses A, B, and C, the multiplexer MUX2 outputs the write address output circuit. The write addresses A, B, and C of 30 are applied to the memory 61. In this case, the pixel address output unit 63 outputs the pixel address according to the pixel clock of the pixel clock output unit 62, and the memory 61 drives in the recording mode when the pixel clock is at a high level. 61 stores pixel data applied through the buffer B2 at pixel addresses in the line addresses A, B, and C, respectively. For example, if a write address signal A is applied from the multiplexer MUX2, the memory 61 inputs 36 pixel data into a line address A to the pixel data inputted from the pixel address output unit 63. It is stored according to the address. In this case, since the pixel data applied to the memory 61 is a parallel scan method, the memory 61 stores 36 pixels of the line 10 in the address A as shown in FIGS. 3 and 4. The pixels of lines 2, 4, 12, and 14 are respectively stored in the recording addresses B and C in synchronization with the horizontal synchronization signal. (The above example is an example where the even field is applied first.) .

At the time t1 when the recording address output number 30 outputs the address signal D, the delay circuit 20 outputs the vertical synchronization signal and the horizontal synchronization signal of the delayed AND gate A1. The address output circuit 40 outputs the read address signal stored in synchronization with the horizontal synchronization signal. At this time, the read address output circuit 40 is n Until (n, Since the read address signal corresponding to the line of + n) is output, the read address address circuit 40 outputs the address signals of A, E, B, and F sequentially. That is, when the recording address output number 30 outputs the address D, the read address signal output circuit 40 outputs the address A. At this time, since the clock signal of the delay circuit 20 is applied to the terminal S1 of the multiplexer MUX1, when the clock signal is high level (that is, when the horizontal synchronization signal, the vertical synchronization signal, and the reset signal are high level). The pixel clock of the pixel clock output unit 62 applied to the terminal a is output. The multiplexer MUX2 outputs a write address signal of the write address output circuit 30 when a high level is applied to the terminal S2, and a read address output circuit when the low level is applied to the terminal S2. Since the read address signal of 40 is outputted, the multiplexer MUX2 outputs the write address signal D and the read address signal A in accordance with the pixel clock of the pixel clock output unit 62.

Therefore, the memory 61 stores the pixels of the line 16 inputted to the address corresponding to the write address signal D when the pixel clock is high level, and the read address when the pixel clock is low level. The pixel data of the line 10 stored in the address A corresponding to the signal A is outputted. In this way, after the pixel data of the lines 10 and 16 are stored and outputted, a low level vertical synchronization signal will be applied through the AND gate A1. Accordingly, the memory 61 is in a disabled state, and the write address output circuit 30 recognizes the remaining address signals as a mode of sequentially outputting the remaining address signals, e. To output E, F, E, F. At this time, since the horizontal address signal (ie, the clock signal by the clock output circuit 10) is applied to the read address output circuit 40, the address signals of E, B, and F are continuously output. Therefore, when a write address E and a read address E are applied to the memory 61, the memory 61 stores pixel data of a line l1 input to the address E in synchronization with the pixel clock. While the data is output again, the pixel data of the line l1 is output through the buffer B1. At this time, when the write address output circuit 30 outputs the write address F, and the read address output circuit 40 outputs the read battery B, the memory 61 is input to the address F. The pixel data of (13) is stored, and the address of the line l2 stored in the address B is output. Also, when the write address E and the read address F are applied to the memory 61, the memory 61 stores the pixel data of the input line l5 in the address E and stores the address data in the address F. The pixel data of the line l3 is outputted. In this case, since the vertical synchronous signal is applied from the delay circuit 20 at the time t2 when the write address output circuit 40 outputs the address F, the read address output circuit 40 is n. Until , the read address signal corresponding to n 1 feed line number + n) is output.

That is, the read address output circuit 40 sequentially outputs the address signals C, E, D, and F. Therefore, when the write address output circuit 30 outputs the write address E, when the read address output circuit 30 outputs the write address E, the read address output circuit 40 reads the read address. Address (C) will be output. Therefore, the memory 61 outputs the pixel data of the line l4 stored in the address C, and stores the pixel data of the input line l7 in the address E. At this time, since the vertical address signal is applied after the recording address output circuit 30 outputs the recording address E, the recording address output circuit 30 outputs the address address first outputted in the same order as the output address. will be. That is, the write address output circuit 30 outputs the write addresses A, B, C, D, E, F, E, and F again in synchronization with the horizontal synchronizing signal. At this time, the read address output circuit 40 outputs the read addresses C, E, D, F, and then horizontally reads the read addresses A, E, B, F which were initially output by the vertical synchronization signal. It is outputted again in synchronization with the synchronization signal. Thus, as shown in FIG. 3, it can be seen that the memory 61 outputs pixel data input by the parallel scan method in a forward scan method.

In the above-described embodiment, the delay circuit 20 is configured to delay the clock and vertical synchronization signals during the time that pixel data corresponding to the (field line number-1) is input to the memory 61, but is shown in FIG. As described above, the memory 61 traverses the pixel data input in a parallel scan manner such that the delay circuit 20 delays the clock and vertical synchronization signals for the time when the pixel data corresponding to one field is input to the memory 61. It can be seen that the output can be converted to the scanning method.

However, it may be preferable that the delay circuit 20 delays the clock and the vertical synchronization signal by the number of lines of the field -1 because it results in a change of the fast scan method to the forward scan method by one line.

As described above, the read address output circuit designates a read address capable of outputting the pixel data of a parallel scan method stored in a predetermined address by the write address output circuit in a forward scan method, and the write address output circuit is provided to the read address. By storing the newly applied line scan data at the line number output by the line address, the memory having a 3/4 frame capacity can convert the scan scan method to the forward scan method.

Claims (7)

A digital image processing apparatus comprising: clock output means for combining a horizontal synchronous signal and a vertical synchronous signal to output a clock signal; Delay means for delaying and outputting a vertical synchronization signal and a clock of the clock output means by a predetermined time; Number of lines in field 1 The recording address signal corresponding to the recording address is sequentially stored, and after the output of the recording address signal which sequentially designates a line of one field in synchronization with the clock of the clock output means according to the vertical synchronization signal, the remaining recording address signals are sequentially performed twice. Recording address output means for continuously performing a process of outputting; Read address signals which designate the same addresses as the recording address output means are sequentially designated, and n is synchronized with the clock of the delay means according to the vertical synchronization signal of the delay means. Until (n, + n) After sequentially reading the read address signals corresponding to (n = 1, 2, 3…), n is Until read address output means for sequentially outputting read address signals corresponding to + n, the total number of lines of one field + n); Selecting means for the recording address output means to selectively output the recording address signal and the read address signal in synchronization with the pixel clock according to the recording address signal and the read address signal according to the delay means and the clock signal; Number of lines in 1 field A line corresponding to the address, and storing the line image data at the address corresponding to the recording address of the selection means in synchronization with the pixel clock, and storing the line image data at the address corresponding to the read address signal of the selection means. A scanning method switching device of a digital image processing apparatus having a storage means for outputting image data. The scanning method switching device according to claim 1, wherein the clock output means comprises an AND gate. The scanning method switching device of claim 1, wherein the delaying time is a time corresponding to the number of lines -1 in one field. The scanning method switching device of the image processing apparatus according to claim 1, wherein the delay time of said delay means is a time corresponding to one field. The method of claim 1, wherein the selecting means is configured to selectively output a high level applied to the pixel clock applied to the first input terminal or the second input terminal according to the main direct synchronization signal of the delay means applied to the selection terminal. 1 multiplexer; A scanning method of a digital image processing apparatus having a second multiplexer for selectively outputting a write address signal of the write address output means or a read address of the read address output means in accordance with an output of the first multiplexer applied to a selection terminal. Switching device. 2. The apparatus of claim 1, wherein the storage means comprises: pixel clock output means for oscillating a pixel clock of a predetermined frequency; Pixel address output means for sequentially outputting pixel address signals synchronized with the pixel clock; Is enabled according to the clock of the clock output means, and stores the image data input according to the pixel clock in the pixel address of the pixel address output means in the line address corresponding to the write address signal of the selection means, and the selection A memory for outputting pixel data stored at the pixel address of the pixel address output means in the line address corresponding to the read address signal of the means; And an input / output state control means for controlling a state in which pixel data is inputted and outputted into the memory in accordance with the pixel clock of the pixel clock output means. 5. The apparatus of claim 4, wherein the input / output state control means comprises: a first buffer which outputs image data of the memory in accordance with a clock of the clock output means; And a second buffer for applying the image data input to the memory in accordance with a clock of the clock output means.