KR940000962Y1 - Apparatus for controlling sub-screen signal of picture-in-picture tv system - Google Patents

Abstract

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Description

Sub picture signal control circuit of screen insertion device

1 is a conventional control circuit diagram.

2 is an explanatory diagram showing the principle of reduction of the sub picture.

(A)-(c) of FIG. 3 is explanatory drawing which shows the relative field switching signal of a mother screen signal and a mother screen signal.

4 is an explanatory diagram showing a joint line phenomenon.

5 is an explanatory diagram showing a vertical solute phenomenon.

6 is a control circuit diagram of the present invention.

7 is a detailed view of the memory controller of FIG.

(A)-(g) of FIG. 8 is a waveform diagram of each part of FIG. 6 and FIG.

(A)-(g) of FIG. 9 are waveform diagrams of each part of FIG. 6 and FIG.

The present invention reduces the sub picture signal and inserts it into the main picture signal, that is, in a device such as a digital video cassette recorder having a picture in picture (PIP) function and a digital television receiver, the sub picture signal is stored in a memory. The present invention relates to a sub picture signal control circuit of a screen inserting device for storing and outputting.

The conventional control circuit includes an input selection switch 1 for selectively outputting a sub picture signal as shown in FIG. 1, and a single port memory for writing and reading a signal passing through the input selection switch 1; 2-5), an output selection switch 6 for selecting and outputting an output signal of the single port memory 2-5, a data switching control unit 7 for controlling the input selection switch 1, and the An address controller 8 for controlling the address of the single port memory 2-5 and a data switching control section 9 for controlling the output selection switch 6 are constituted.

In the conventional control circuit configured as described above, when the magnetic screen signal is input and applied to the movable terminal of the input selection switch 1, the control unit of the data switching control unit 7 switches the input selection switch 1 and is applied to the movable terminal. The screen signal is selectively output, and the sub picture signal output from the input selection switch 1 is written to the single port memory 2-5 under the control of the address controller 8, and is read when the writing is completed, and the single port The sub picture signal read out from the memory 2-5 is selected and outputted while the output selection switch 6 is switched under the control of the data switching controller 9.

Here, the principle of reducing the signal of the sub-screen in the screen insertion device is as follows.

Assuming that the screen of the original magnetic screen signal is not reduced (a) of FIG. The case to be reduced in the lateral side of the sample the sample one pixel from three pixels that is, 1C, 4C and 7C row, and the vertical axis indicates the samples the sampled one line in three lines i.e., 1L, 4L and 7L line f _CS When the signal written to the memory is read at the speed of 3f _SC , the screen of the magnetic screen signal is formed as shown in (b) of FIG. 2 so that the magnetic screen is vertically and horizontally. Will be reduced.

When (a) of FIG. 3 is a relative pulse switching signal of the mother screen signal, and (b) of FIG. 3 is a relative pulse switching signal of the child screen signal, the field data of the child screen is measured at time tl. The field data of the sub picture written in the memory is read from the time t2 to the time t4 while being written to the memory between the time t5, wherein the sub picture signal is changed from (a) of FIG. b), the read speed of the memory is faster than the write speed.

That is, since the read address of the memory is faster than the write address at time t3, the subfield signal of the new field is output before the time t3, and the subfield signal of all the fields is output after the time t3. As illustrated in FIG. 4, a joint line phenomenon occurs in which an upper middle part and a lower middle part of the screen are shifted.

Then, as shown in FIG. 5 (a) (b) In the subscreen having a vertical distance of H (here, H is the frequency of the vertical synchronization signal), since the phase difference does not flow uniformly between the parent screen and the subscreen, the odd and even fields of the subscreen signal and the odd and excellent values of the parent screen signal When the field is synchronized and when it is not synchronized, it may appear irregularly on the screen. Such a phenomenon is caused by a vertical joit phenomenon, which causes the screen to shake up and down.

In order to eliminate the joint line phenomenon and the vertical salt phenomenon, the conventional control circuit as described above requires a large number of memories and an input selection switch and an output selection switch. And a large number of parts are consumed and the production cost of the product is increased.

The present invention uses four field memories for storing one field of data in view of the above-described defects, and controls the four field memories to naturally synchronize the mother screen signal with the sub picture signal. A memory controller of the present invention is described in detail with reference to the accompanying drawings of FIGS. 6 to 9 as follows.

6 is a control circuit diagram of the present invention, in which the odd field memory (11) 12 (12) which independently and simultaneously writes and reads data of the odd field of the inputted sub picture signal, Even field memory (13) (14), which independently writes and reads data of even field, and the odd field memory (11) (12) and even field memory (13) by synchronizing the sub picture signal and the parent picture signal. (14) is configured as a memory controller (15) for controlling.

And, the seventh turn a detailed view of the sixth degree memory controller 15, thus forcing the horizontal synchronizing signal (HD ₁₎ to be input as illustrated chair detects the screen signal and the horizontal and vertical synchronizing signals of the main screen signal ( HD ₂ ) and forced vertical synchronous signal (VD ₁ ) (VD ₂ ) are output as well as the forced horizontal synchronous signal (HD ₁ ) (HD ₂ ). Forced synchronous signal and clock signal generators 151 and 152 for delaying H and outputting clock signals CLK ₁ and CLK ₂ , and output signals of the forced synchronous signal and clock signal generators 151 and 152. Odd / excellent field discriminating units 153 and 154 comprising flip-flops FF ₁ and FF ₂ (FF ₃ and FF ₄ ) for discriminating the odd and even fields of the sub picture and the parent picture according to Control signals CS ₁ and CS ₃ of the gas field memories 11 and 12 and the even field memories 13 and 14 in accordance with the output signal of the non-field determining unit 153 and 154 and the sub picture output time signal. , A control unit 155 including a flip-flop (FF ₅ -FF ₇ ) and an AND gate (AND) for outputting CS ₄ ).

In the drawings of FIG. 7, reference numeral Vcc denotes a power supply terminal, D ₁ -D ₄ , T ₅ , D ₆ , and D ₇ are input terminals, and RST ₁ and RST ₃ are reset terminals, and Q ₁ and Q _2. , Q ₃ , Q ₄ , Q ₅ , Q ₆ and Q ₇ are output terminals and CK _1- CK ₇ are clock terminals.

The operational effects of the present invention constructed as described above will be described with reference to the waveform diagrams of FIGS. 8 and 9.

When power is supplied to the power supply terminal Vcc and the sub picture signal and the mother screen signal are respectively input to the forced synchronization signal and the clock signal generator 151 and 152, the forced synchronization signal and the clock signal generator 1 51 152 is an eighth-degree (a) to output a clock signal (CLK ₁₎ (CL K _2), as shown in the flip-flop (FF _1), a clock terminal (CK ₁₎ of (FF ₃₎ (CK ₃₎ It is also as well as the reset terminal of the flip-flop (FF1) (FF3) and outputting a forced horizontal synchronizing signal (HD ₁₎ (HD ₂₎ as shown in degrees of claim 8 (b) to (RST ₁₎ (RST ₃ ), The flip-flop FF ₁ (FF ₃ ) is reset according to the forced horizontal synchronization signal HD ₁ (HD ₂ ), and according to the clock signal CLK ₁ (CLK ₂ ), FIG. Output terminal as shown in Outputs a pulse signal to the input terminal D ₂ (D ₄ ) of the flip-flop (FF ₂ ) (FF ₄ ), where the forced synchronization signal and the clock signal generators 151 and 152 of FIG. As shown in (d) of FIG. 8, the forced horizontal synchronization signal HD ₁ and HD ₂ output as shown in (b) according to the odd and even fields of the sub picture signal and the parent picture signal. When applied to force the clock terminal (CK ₂₎ (CK ₄₎ of the vertical synchronization signal (VD ₁₎ and outputting (VD ₂₎ flip-flop _{(FF 2) (FF 4)} , the flip-flop (FF ₂₎ (FF ₄₎ Outputs a pulse signal to the output terminals Q ₂ and Q ₄ as shown in (e) of FIG. 8, and as shown in (f) of FIG. H after the is applied to a clock terminal (CK ₂₎ (CK ₄₎ of the flip-flop (FF ₂₎ (FF ₄₎ to output a force vertical synchronizing signal _{(VD 1) (VD 2)} , flip-flop (FF ₂₎ FF ₄ outputs a pulse signal to output terminals Q ₂ and Q ₄ as shown in FIG. 8 (g).

As such, the clock signal CLK ₁ (CLK ₂ ), the forced horizontal synchronization signal HD ₁ , HD ₂ , and the forced vertical synchronization signal VD ₁ outputted from the forced synchronization signal and the clock signal generators 151 and 152. If the flip-flops FF ₂ and FF ₄ output pulse signals to the output terminals Q ₂ and Q ₄ in accordance with VD ₂ , as shown in FIGS. flop output signals (FF ₂₎ are so applied to the clock terminal (CK ₅₎ of the output tray as well as a flip-flop (FF ₅₎ a control signal (CS ₂₎ a flip-flop (FF ₅₎ is outputted to the output terminal (Q ₅₎ As shown in FIG. 9C, the control signal CS ₁ is outputted, and the control signal CS ₁ is applied to the input terminal D ₆ of the flip-flop FF ₄ . The output signal of FF ₄ ) is applied to one input terminal of the AND gate AND and the input terminal CK ₇ of the flip-flop FF ₇ .

At this time, as shown in (d) of FIG. 9, when the sub picture display time signal is input and applied to the other input terminal of the AND gate AND and the clock terminal CK ₇ of the flip-flop FF ₇ , the AND gate ( AND outputs a pulse signal and applies it to the clock terminal CK ₆ of the flip-flop FF ₆ as shown in (e) of FIG. 9, so that the flip-flop FF _{7 is} shown in (f) of FIG. As shown, the control signal CS ₃ is output to the output terminal Q ₆ , and the flip-flop FF ₇ is the control signal CS ₄ to the output terminal Q ₇ as shown in (g) of FIG. 9. The control signals CS _{1 to} CS ₄ output in this way are applied to the field memories 11-14 to control the write and read operations of the field memories 11-14.

Here, the control signal CS ₂ is a signal indicating a field of the sub picture signal, and if the control signal CS ₂ has a high potential, it represents an even field, and if it is a low potential, a control field CS ₁ is represented. Is a divided signal of the control signal CS ₂ , one of the four field memories 11-14 is selected by the control signals CS ₁ , CS ₂ to select the field data of the sub picture signal, The control signal CS ₃ selects a field to riddle the field data, and the control signal CS ₄ is a signal for discriminating the field of the parent screen signal from the sub-screen display time signal. The control signals CS ₃ and CS ₄ select one of the four field memories 11-14.

Therefore, the odd and even field data of the sub picture signal reduced and output coincides with the odd and even field of the parent picture signal, and the field written in the field memory 11-14 in which the field data of the sub picture signal is not written. Since the data is read, the joint line phenomenon and the vertical salt phenomenon do not occur on the magnetic screen.

At this time, the control signals CS ₁ and CS ₂ indicate the addresses of the field memories 11-14 to which the sub picture signal is to be written, and the control signals CS ₃ and CS ₄ indicate the field memo to be read 11-14. The address of the four field memories 11-14 is shown in Table 1 below, and the address of each field controlled by the control signals CS ₁ and CS _{4 is} shown in Table 2 below.

TABLE 1

TABLE 2

As described in detail above, the present invention requires a small number of memories to be used, and there is no need to use an input and output selection switch as in the prior art, and a control unit for controlling the switch is also simplified, thereby making the whole system very simple. Therefore, the cost of producing the product is reduced.

Claims (1)

It detects the horizontal and vertical synchronization signals of the sub-screen signal and the parent screen signal and outputs the forced horizontal and forced vertical synchronization signals HD ₁ (HD ₂ ) and (VD ₁ ) (VD ₂ ). Sync signal (HD ₁ ) (HD ₂ ) According to the output signal of the forced synchronous signal and clock signal generator 151, 152 for delaying H and outputting the clock signal CLK ₁ (CLK ₂ ), and the forced synchronous signal and clock signal generator 151, respectively. According to the output signal of the odd / excellent field discrimination unit 153 for outputting the control signal CS ₂ for discriminating the odd and even field of the screen signal and the forced synchronization signal and the clock signal generator 152, The control signal CS ₂ is divided according to the radix / excellent field discriminating unit 154 for discriminating the number and the excellent field and the output signal and the sub-screen display time signal of the / excellent field discriminating unit 153 and 154. A control unit 155 for outputting a control signal CS ₁ , a control signal CS ₃ for selecting a field to be read, and a control signal CS ₄ for discriminating a field of the parent screen signal to the sub picture display time signal; said control signal light and lead to the nose and the even field of data signal sub screen input according to (CS ₁ -CS ₄₎ The odd field memory 11, 12 and even field memory of the display device, characterized in that the insert consists of a (13, 14) sub screen signal control circuit.