KR890011430A - Black and white still picture recording and playback circuit - Google Patents

Black and white still picture recording and playback circuit Download PDF

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Publication number
KR890011430A
KR890011430A KR1019870015545A KR870015545A KR890011430A KR 890011430 A KR890011430 A KR 890011430A KR 1019870015545 A KR1019870015545 A KR 1019870015545A KR 870015545 A KR870015545 A KR 870015545A KR 890011430 A KR890011430 A KR 890011430A
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KR
South Korea
Prior art keywords
signal
horizontal
vertical
window
output
Prior art date
Application number
KR1019870015545A
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Korean (ko)
Other versions
KR910001220B1 (en
Inventor
장주욱
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870015545A priority Critical patent/KR910001220B1/en
Publication of KR890011430A publication Critical patent/KR890011430A/en
Application granted granted Critical
Publication of KR910001220B1 publication Critical patent/KR910001220B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/78—Television signal recording using magnetic recording
    • H04N5/782—Television signal recording using magnetic recording on tape
    • H04N5/783—Adaptations for reproducing at a rate different from the recording rate

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

내용 없음No content

Description

흑백 정지화상의 기록 및 재생회로Black and white still picture recording and playback circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 정지화상의 기록 및 재현회로.3 is a recording and reproducing circuit of a still image according to the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 클럭발생회로 20 : 동기분리회로10: clock generation circuit 20: synchronization separation circuit

30 : 수평수직 왼도우 발생회로 40 : 프리지 인에이블회로30: horizontal vertical left generating circuit 40: free enable circuit

50 : 화상 입출력 제어회로 60 : 복합동기신호 발생회로50: image input / output control circuit 60: composite synchronous signal generating circuit

70 : 화상 기록/재현회로70: image recording / reproduction circuit

Claims (1)

흑백 정지화상의 기록 및 재생회로에 있어서, 시스템 동작에 필요로 하는 클럭을 출력하는 클럭발생회로(10)와, 입력 복합영상신호에서 등화펄스가 포함되는 수평동기펄스(HS)와 수직동기펄스(VS)를 분리하는 동기분리회로(20)와, 상기 분리출력되는 수평동기펄스(HS)와 수직동기펄스(VS)를 변형하여 화면의 수평/수직의 크기 및 위치를 결정하는 수평윈도우(HSW)와 수직윈도우(VSW)를 출력하는 동시에 수직윈도우(VSW)내에 있는 수평윈로우(HW)와 시스템 클럭앤딩하여 화면 표본클럭(VCLK)로 출력하는 수평수직 윈도우 발생수단과, 기록 제어신호 스위칭시에 1피일드의 신호를 기록할수 있는 프리지 인에이블 신호를 출력하는 프리지 인에이블발생 수단과, 상기 수평수직 윈도우신호 발생수단으로 부터 출력하는 화면 표본클럭(VCLK)에 의해 일정주기의 메모리 칩셀렉터신호를 발생하고 상기 프리지 인에이블의 논리에 따라 상기 메모리칩셀렉터 신호를 기록 또는 재생출력 제어신호로 선택 출력하는 화상 입출력 제어수단과 일측입력으로는 동기신호 레벨을 또다른 일측 입력으로는 상기 동기신호 레벨보다 소정 레벨이 높은 직선소자 레벨의 신호를 입력하고 이를 상기 동기분리회로(20)에서 출력되는 수평 동기신호(HS)에 의해 선택하여 복합동기신호를 발생 출력하는 복합동기신호 발생회로와, 입력영상 신호를 디지탈화하여 상기 영상입출력 제어회로의 제어에 따라 내장된 메모리에 기록하고 재생하여 출력하는 화상데이터 입출력 수단과 상기 수평수직 윈도우 발생수단에서 출력되는 화면 표본클럭(VCLK)신호를 카운팅하여 상기 화상데이터 입출력 수단내의 메모리의 열어드레스를 제공하는 동시에 상기 수평수직 윈도우 발생수단에서 출력되는 수평윈도우 신호를 카운팅하여 상기 메모리의 행어드레스를 제공하는 어드레스 발생수단으로 구성함을 특징으로 하는 회로.In a black and white still picture recording and reproducing circuit, a clock generating circuit 10 for outputting a clock required for system operation, a horizontal synchronizing pulse (HS) and a vertical synchronizing pulse including equalization pulses in an input composite video signal ( VS) and a horizontal window (HSW) for deciding the horizontal / vertical size and position of the screen by modifying the horizontal and vertical sync pulses (HS) and the vertical sync pulses (VS). And a vertical window generating means for outputting a vertical window (VSW) and a horizontal window (HW) in the vertical window (VSW) and a system clock-ending to output the screen sample clock (VCLK). Memory chip of a certain period by free enable generation means for outputting a free enable signal capable of recording a one-feed signal, and a screen sample clock (VCLK) outputted from the horizontal vertical window signal generation means. Image input / output control means for generating a selector signal and selecting and outputting the memory chip selector signal as a recording or reproducing output control signal according to the logic of the free enable, and with one input, a synchronization signal level. A composite synchronous signal generating circuit which inputs a signal of a linear element level higher than a synchronous signal level and selects it by the horizontal synchronous signal HS output from the synchronous separation circuit 20 to generate and output a composite synchronous signal; And counting screen sample clock (VCLK) signals outputted from the horizontal and vertical window generating means by digitalizing the input image signal, recording, reproducing, and outputting it in an internal memory under the control of the image input / output control circuit. Providing the opening dress of the memory in the image data input / output means and simultaneously And address generating means for counting a horizontal window signal output from the vertical window generating means and providing a row address of the memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870015545A 1987-12-31 1987-12-31 Recording and play back circuit of black still picture KR910001220B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870015545A KR910001220B1 (en) 1987-12-31 1987-12-31 Recording and play back circuit of black still picture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870015545A KR910001220B1 (en) 1987-12-31 1987-12-31 Recording and play back circuit of black still picture

Publications (2)

Publication Number Publication Date
KR890011430A true KR890011430A (en) 1989-08-14
KR910001220B1 KR910001220B1 (en) 1991-02-26

Family

ID=19267817

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870015545A KR910001220B1 (en) 1987-12-31 1987-12-31 Recording and play back circuit of black still picture

Country Status (1)

Country Link
KR (1) KR910001220B1 (en)

Also Published As

Publication number Publication date
KR910001220B1 (en) 1991-02-26

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