KR0130437B1 - Method of data storage into a memory in a 6-divided decoder for mpeg2 - Google Patents

Abstract

A method for improving memory structure of an MPEG 26 divided decoder is disclosed. The method consists of a step of arranging three rows to the left side of a frame image map in case of even slices and arranging three rows to the right side of the frame image map in case of odd slices; and a step of converting the position on the frame image to a frame memory address. Thereby, the converting can be easily performed and the access time can be reduced.

Description

Memory structure improvement method in MP2 6 split decoder

1 is a schematic diagram showing a sequential storage method.

2 is a schematic diagram of a storage method combining regular array and decoding.

3 is a diagram illustrating a problem of a storage method in which regular arrays and decoding are combined.

4 is a schematic diagram showing a frame image storage structure according to the present invention.

5A and 5B show the shape of a memory address vector for forming the structure shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory structure in an MPEG2 6 split decoder, and more particularly, to a method of improving a memory structure in an MPEG2 6 split decoder having a frame image storage structure.

In a typical six split decoder, six blocks, i.e., Y1, Y2, Y3, Y4, U, V, and blocks, are processed simultaneously in each module.

Therefore, each module has the same address structure with 8x8 blocks as macroblocks.

In general, for HDTV single-screen frames with a resolution of 1920X1080 pixels, 120X68 macroblocks must be stored in memory for each module. At this time, one pixel is 8 bits, and one macroblock has a size of 64 bytes, so a total of 32 macroblocks are included in a row in a 512 × 512 DRAM having a size of 32 bits.

Since one slice (SLICE) of the frame of the DHTV screen is composed of 120 macroblocks, it takes 3.75 rows to store one slice in memory. That is, it occupies as many as 24 macroblocks in the third row memory and the fourth row.

In such a state, the frame image data is stored in the memory. In the related art, there is a method of combining the sequential storage method, the regular arrangement, and the decoding.

First, the sequential storage method illustrated in FIG. 1 will be described.

The sequential storage method stores the pixel data in the memory in the order of the macroblocks appearing on the MPEG2 video bitstream. 1 shows this on a frame image map.

The problem with this method is the process of obtaining the actual memory address from the calculation result on the frame image when reading a macroblock on the reference frame memory by adding the motion vector to the base address during motion compensation in MPEG2 decoding. The complex process of dividing in and so on takes a long time.

In addition, the method of combining regular array and decoding is as follows.

In practice, there are a variety of ways to implement regular arrays, but the basic method is to simplify the conversion of the position in memory from the position of the frame image by making the addressing unit a multiple of 2.

However, since the structure of the frame image data is 1920 × 1080 pixels or 120 × 68 macroblocks, it cannot itself be a multiple of two.

Therefore, in order to use the memory efficiently, decoding logic (LOGIC) which performs address mapping to the part having a regular arrangement and the remaining part is required.

As shown in FIG. 2, dividing a row into four 8 microblock sections SECTION can store one slice as 8 × 15.

The other section decodes and maps the later missing address portion.

The problem with this method, as shown in FIG. 3, is that when a macroblock is placed anywhere on the reference image, it can pick up a cross-shaped row change in memory.

The cross-shaped row change is the worst case, in which case a total of four row changes occur, which causes a delay in the access time (ACCESS TIME) of the DRAM structure.

The present invention has been devised to solve the above problems, and an object of the present invention is to provide an MPEG26 split decoder capable of reducing access time through a new frame image storage structure in a frame memory using DRAM. To improve the memory structure of the present invention.

In order to achieve the object as described above, the present invention is to align three rows to the left of the frame image map in the even slice, to the right of the frame image map in the odd slice and to the right of the frame image map in the odd slice And converting from a position on the frame image of the step to a frame memory address.

Below. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic diagram showing a frame image storage structure according to the present invention.

As shown in FIG. 4, the present invention is designed to reduce the number of four row changes that can be obtained in the conventional regular arrangement and not to require complicated address generation as in sequential storage.

In general, in the DRAM frame memory, no matter what structure is selected, in the worst case, up to three row changes may occur.

The third row change occurs when the row boundary meets the form of 'TT'. Also, in HDTV, one slice occupies 3.75 rows.

Therefore, as shown in FIG. 4, if three rows are aligned to the left of the frame image in the even slices and to the right of the frame image in the odd slices, a boundary of a row of 'TT' or 'ㅗ' shape is always obtained. Can be.

At this time, the right 24 microblocks in the even slices and the left 24 microblocks in the odd slices are stored at the back of the memory, and when addressing the parts, the addresses are mapped through decoding logic as in the conventional regular array and decoding.

5A and 5B show the form of a memory address vector for forming the structure shown in FIG.

5A shows a column COLUMN portion of the memory address vector.

In FIG. 5A, the first one bit represents ACCESS PARITY, and the next three bits represent a line number in the macroblock. In addition, the remaining 5 bits indicate the number of macroblocks in the row.

In the above, the access parity is a 32-bit, i.e., 4 pixels bandwidth, so that one line of 8 pixels is divided into left and right in a macroblock of Hanan, and indicates whether the left side is read or the right side is read.

5B shows the row portion of the memory address vector.

In FIG. 5B, the first 2 bits represent the row number in the slice, the next 6 bits represent the slice number in the frame, and the remaining 1 bit represents the frame number.

As described above, the present invention has an effect of reducing access time since the conversion from the position on the frame image to the frame memory address is simple and the line boundary is formed in the form of 'TT' or 'ㅗ'.

Claims (2)

Aligning three rows to the left of the frame image member in the even slices and to the right of the frame image map in the odd slices; And converting the frame memory address from the position on the frame image of the step. 2. The method of claim 1, wherein the frame memory address vector has a column vector in which the first 1 bit is access parity, the next 3 bits are line numbers in the macroblock, and the remaining 5 bits are numbers of the macroblocks in the row. The first 2 bits are the row number in the slice, the next 6 bits are the slice number in the frame, and the last 1 bits are the row vector roll. A method for improving the memory structure in an MPEG2 six-segment decoder characterized by the above-mentioned.