KR100565713B1 - Address generating Method for compensating motion of image - Google Patents

Abstract

The present invention relates to a method for generating an image motion compensation address capable of generating a memory access address with a small number of gates in a motion compensation operation in processing video data. Addresses required for reading and finally summing and storing the data of the IDCT buffer storing the converted data and the MC buffer storing the motion compensated data are divided according to the image type of the luminance / color difference signal, and the frame type according to the compression / display mode. It is classified into (fr) and field type (fd), and the bit order of the read or write count signal is changed and used.

Description

Address generating method for compensating motion of image

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the processing of moving image data, and more particularly, to a method for generating an address for image motion compensation in which a memory access address can be generated with a few gates in a motion compensation operation.

In general, a motion compensation unit is essential for efficient compression of massive video information in a decoding apparatus that compresses and restores a large amount of video information in high-definition TV, CATV, video conferencing, video telephony, and the like. The operation of reading or writing image information is often performed.

Hereinafter, a final sum block of pixel data for motion compensation in a decoder according to a typical moving picture expert group 2 (MPEG-2) will be described with reference to the accompanying drawings.

1 is a block diagram of a pixel data final summation block for motion compensation in a decoder according to MPEG-2.

The decoder performs a motion compensation operation to restore the compressed and transmitted image data. An IDCT buffer 11 for storing inverse DCT changed pixel data and a motion compensation buffer unit 12 for storing motion compensated pixel data. ) And 36 bits of inverse DCT transformed data of the IDCT buffer unit 11, that is, 9-bit pixel data, are read in macroblock units, and 8 bits of motion compensated pixel data of the MC buffer unit 11, that is, 8 bits. Final accumulator buffer 13 storing a plurality of accumulating blocks 14 for reading and finally adding 32-bit pixel data of a size in macroblock units and a final summed pixel data output from the accumulating blocks. And a final summing block comprising bus lines used to transfer data between these blocks.

The concept of the final summing operation of the decoder configured as described above is as follows.

FIG. 2 is a diagram illustrating an operation concept of a final summing block, and FIG. 3 is a diagram illustrating a structure in which data in macroblock units is mapped to an actual memory.

As shown in FIG. 2, the final summation block of the decoder reads the inverse DCT transformed data from the inverse discrete cosine transform (IDCT) buffer in macroblock units and reads and adds motion compensated data in macroblock units in the MC buffer to add the FADD buffer. Perform the operation of saving to.

In the pixel data summing operation in units of macro blocks, pixel data is mapped to an actual memory as shown in FIG. 3.

Processing data in units of macro blocks means that four pixel data are stored in one address.

In the final summation block of the decoder, an address for reading four pixel values in the IDCT buffer and an MC buffer and an address for writing four pixel data in the FADD buffer must be different according to the type of picture.

The operation timing of the final summation is as follows.

4A is a summation operation timing diagram for the luminance signal in the final summation block, and FIG. 4B is a summation operation timing diagram for the color signals in the final summation block.

FIG. 4A illustrates the final addition operation timing in the case of a luminance signal in units of half MB in the normal mode, and FIG. 4B illustrates an interleaved 16 * 8 Cb and Cr block in the normal mode. The final summing operation timing of the chrominance signal is shown.

In the MPEG-2 decoder, 16 (horizontal) x 16 (vertical) pixels are most commonly used as macroblocks, and one pixel of image information is one byte of memory for luminance signals. Corresponds to the capacity.

If it is assumed that the memory segment unit of the frame memory is 8 byte unit, one address is allocated in 8 byte unit which is one segment, and 8 pixel image information can be stored per segment, so that 8 pixels of image can be stored at a time. The information is accessed and read or written.

As such, in order to compensate for the motion, the memory input data stored in the frame memory is read and added to the predictive data to be compensated for inversely transformed by the image decoder.

In addition, since the unit of reading or writing image information from the memory is 8 pixels, when performing motion compensation when the number of pixels constituting a single screen is large, data must be exchanged at a very high speed between the decoder and the memory. And a lot of power consumption for the memory interface at the decoder.

In the conventional motion compensation operation according to the MPEG-2, the following problem occurs when the IDCT pixel value and the pixel value for which motion compensation is performed are added in macroblock units.

When the pixel value is added in units of macroblocks, the gate structure for generating an address for accessing the buffer memory is complicated, and thus there is a problem in that the total chip area is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for generating an address for image motion compensation, which can simplify the configuration of a memory address generation block of a conventional decoder.

In the method of generating an image motion compensation address according to the present invention which simplifies a memory address generation block, an IDCT buffer for storing IDCT-converted data and an MC buffer for storing motion-compensated data in reconstruction of an image compressed signal according to MPEG 2 The data required to read and finally add and store data is divided according to the image type of the luminance / color difference signal, and classified into the frame type (fr) and the field type (fd) according to the compression / display mode. It is characterized by changing the order of bits.

Hereinafter, an address generation method for image motion compensation according to the present invention will be described in detail with reference to the accompanying drawings.

5A through 5C are state diagrams illustrating a chrominance signal summing process when both IDCT data and MC data are present according to the present invention.

The address generation method according to the present invention is to change the bit order of the read counter signal read_cnt and the write counter signal write_cnt to generate the read access address and the write access address of each buffer.

That is, to provide a new address generation standard according to MPEG-2.

The generation of such an access address varies depending on the type of picture.

First, the image is divided into a luminance image and a chrominance signal according to the type of image.

Second, it is classified into a frame type (fr) and a field type (fd) according to the compression / display mode.

The method of generating an address at the time of summing IDCT + MC = FADD is classified as follows.

First, in the case of a luminance image,

First, when pixel data is stored in IDCT and MC buffers as field-based images, summed data is stored in the FADD buffer only in field units with each I, P, and B image as fd + fd = fd.

At this time, the read address types of the IDCT buffer and the MC buffer are LRAT 1 (Luminance Read Address Type 1).

Second, when pixel data is stored in the IDCT and MC buffers as frame-by-frame images, the sum data is stored in the FADD buffer only in units of frames with I and P images as fr + fd = fr.

At this time, the read address type of the IDCT buffer is LRAT 1 and the read address type of the MC buffer is LRAT 2.

In addition, the summed data is stored in the FADD buffer in units of fields with the B image as fd + fr = fd.

At this time, the read address type of the IDCT buffer is LRAT 1 and the read address type of the MC buffer is LRAT 3.

In the case of such a luminance image, the read address types may be divided into three types, LRAT 1,2 and 3, and LRAT 1 refers to generating an address using the bit order of the read count (read_cnt) generated as it is. Is used by changing the read count bit order to 1,4,5,3,2,0.

LRAT 3 uses 3, 4, 2, 1, 5, and 0 in reverse read count bit order.

The write address type LWAT changes the bit order of the write count write_cnt to 5, 3, 2, 1, 4, 0.

The reason why the number of count bits is 6 bits is that the motion compensation operation is performed in units of macro blocks.

And in the case of a color difference signal,

First, when Id, B, and P images are stored in the IDCT buffer and the MC buffer as field units of the image, the sum data is stored in the FADD buffer only in field units.

At this time, the read address types of the IDCT buffer and the MC buffer are CRAT 1 (Chrominance Read Address Type 1).

Second, when the pixel data is stored in the IDCT buffer and the MC buffer on a frame basis, the sum data is stored in the FADD buffer only on a frame basis with the I and P images as fr + fd = fr.

At this time, the read address type of the IDCT buffer is CRAT 1 and the read address type of the MC buffer is CRAT 2.

In addition, the summed data is stored in the FADD buffer in units of fields with the B image as fd + fr = fd.

At this time, the read address type of the IDCT buffer is CRAT 1 and the read address type of the MC buffer is CRAT 3.

In the case of such a color difference image, the read address types can be divided into three types, CRAT1, CRAT2, and CRAT3. CRAT1 changes the bit order of the read count (read_cnt) to be generated in order of 5,0,4,2,1,3. The CRAT2 generates an address by changing the read count bit order in the order of 5,0,1,4,2,3.

CRAT3 generates an address by changing the bit order of the read count signal in the order of 5,0,2,1,4,3.

The write address type is used by changing the bit order of the write count (write_cnt) to 4, 5, 2, 1, 3, 0.

As described above, in addition to changing the bit order of the count signal to an arbitrary order and using the address as it is, a lookup table can be created and used for various cases.

5 illustrates a final summation process when data exists in both the IDCT buffer and the MC buffer.

cs0 represents a state in which the cb data of the IDCT buffer and the MC buffer are temporarily transferred to the register, respectively, Icb represents the color difference signal cb of the IDCT buffer, and Mcb represents the color difference signal cb of the MC buffer.

cs1 shows the state of temporarily moving cr data of IDCT buffer and MC buffer to register.

cs2 represents the step of adding the data transferred to the register and loading it on the Wbus.

This operation is repeated until cs3, cs4, ..., cs33, and the motion-compensated data in macroblock units is finally summed.

The method of generating an address for image motion compensation according to the present invention has the following effects.

By using the count signal in the read or write operation of the pixel data, the bit order of the count signal is randomly changed without using an address separately, and the data is summed and stored as it is, so that the access address is generated when the final sum data is stored. The number of gates required can be reduced.

1 is a block diagram of a final sum block of pixel data for motion compensation in a decoder according to MPEG-2

2 is a block diagram showing an operation concept of the final summing block

3 is a diagram illustrating a structure in which data in macroblock units is mapped to a physical memory;

4A is a summation operation timing diagram relating to a luminance signal in a final summation block;

4B is a summation operation timing diagram for color signals in a final summation block;

5A to 5C are state diagrams illustrating a chrominance signal summing process when both IDCT data and MC data are present according to the present invention.

Claims (9)

In the method of generating an address for image motion compensation when restoring a video compressed signal according to MPEG 2, Dividing an address required for reading and finally summing and storing data of an IDCT buffer for storing IDCT-converted data and an MC buffer for storing motion-compensated data according to an image type of a luminance / color difference signal; Classifying the address into a frame type (fr) and a field type (fd) according to a compression / display mode; And And generating an address by changing a bit order of a read or write count signal. The method of claim 1, wherein in the case of the luminance image, when pixel data is stored in IDCT and MC buffers in units of fields, the respective I, P, and B images are summed in units of fields, and the data is stored in the FADD buffer. The address generation method according to claim 1, wherein the read count signal is used as it is. The method of claim 1, wherein in the case of the luminance image, when pixel data is stored in the IDCT and the MC buffer as a frame unit image, the I and P images are summed in units of frames, and the data is stored in the FADD buffer. The read address type of the buffer uses the read count bit order as it is, and the read address type of the MC buffer changes the read count bit order to 1, 4, 5, 3, 2, 0. How it happens. The method according to claim 1, wherein in the case of the luminance image, when pixel data is stored in the IDCT and the MC buffer as a frame unit image, the sum data of the B image is stored in the FADD buffer in field units, and the IDCT buffer read at this time. The address type uses the read count bit order as it is, and the read address type of the MC buffer is 3, 4, 2, 1, 5, 0. The read count bit order is used to change the image motion compensation. How address is generated. The method of claim 1, wherein in the case of the luminance image, the write address type is used by changing the bit order of the write count (write_cnt) to 5, 3, 2, 1, 4, 0. . The method according to claim 1, wherein when the color difference signal is stored in the IDCT buffer and the MC buffer as a field unit image, the respective I, B, and P images are summed by field unit, and the data is stored in the FADD buffer. The read address type of the video motion compensation address generation method, characterized in that for changing the bit order of read count (read_cnt) in the order of 5,0,4,2,1,3. The method of claim 1, wherein in the case of the color difference signal, when pixel data is stored in the IDCT buffer and the MC buffer in units of frames, the I and P images are summed in units of frames, and the data is stored in the FADD buffer. The read address type of is used by changing the bit order of read count (read_cnt) to 5,0,4,2,1,3. The read address type of the MC buffer uses the read count bit order of 5,0,1,4,2. And generating the image motion compensation address in the order of. The method of claim 1, wherein in the case of the color difference signal, when pixel data is stored in the IDCT buffer and the MC buffer in units of frames, the B image is added in units of fields, and the data is stored in the FADD buffer. The address type is used by changing the bit order of read count (read_cnt) in the order of 5,0,4,2,1,3. The read address type of the MC buffer uses the bit order of the read count signal as 5,0,2,1. And generating the image motion compensation address in the order of 4 and 3. The method of claim 1, wherein the write address type is used by changing the bit order of the write count (write_cnt) to 4, 5, 2, 1, 3, 0 in the case of the color difference signal.