KR930004906Y1 - Address assignment system in extended memory - Google Patents

Abstract

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Description

Extended Memory Addressing System

1 is a diagram for explaining a conventional addressing system of a memory.

2 is a view for explaining an addressing system of an extended memory according to the present invention.

3 is a view for explaining the operation of the mode register shown in FIG.

* Explanation of symbols for main parts of the drawings

1: central processing unit 2: valid address generator

3, 6: memory unit 4: expandable memory area

5: Mode register 7: Address decoder

10: address bus 20: data bus

30: control signal bus

The present invention relates to a system for addressing a memory in a single chip microcomputer incorporating a memory, and more particularly, to a system for addressing a memory when a memory is to be expanded beyond a structurally expandable area. It is about.

In general, the addressing mode for program instructions in a microcomputer system includes a direct addressing mode, a direct addressing mode for specifying a register, an immediate addressing mode, and the like. Uses a portion of data memory, usually decorated with S-RAM. Therefore, if you want to add a new register, you need to increase the data memory. In addition, there are many cases where it is necessary to increase the data memory. At this time, if the number of address bits of the CPU is sufficiently large, as shown in FIG. 1, the effective address generator 2 receives the address signal output from the CPU and actually generates an address of the data memory. It is easy to expand the data memory area 4 because only the memory needs to be mounted to the address generation area while maintaining the existing design.

However, in the case of an expandable area that can be implemented as the address bits of the central processing unit, for example, if the address bits are 16 bits, the expansion of the central processing unit as well as the circuit of the idle address generator is necessary. There is also a problem that needs to be changed.

Accordingly, an object of the present invention is to provide an addressing system for an extended memory that allows the memory to be extended beyond an expandable area without changing the structure of an existing chip.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an addressing system for an extended memory according to the present invention, and as shown, an effective address generator 2 connected to an n-bit address bus 10 output from the central processing unit 1 is shown. And a mode register 5 connected to the data bus 20 and the control signal bus output from the central processing unit 1, the n-bit address bus 12 output from the valid address generator 2, and A memory section having an address decoder 7 connected to the m-bit address bus 11 output from the mode register 5, and an expansion memory addressed by an output signal of the address decoder 7; It consists of (6).

Referring to the operation of the addressing system of the present invention expansion memory having the configuration as described above are as follows.

First, the address bus 12 is transferred from the valid address generator 2 by a command outputted from the central processing unit 1 to the valid address generator 2 up to a memory area expandable only by the existing valid address generator 2. This is done by addressing memory.

However, if you want to use more extended memory, that is, if you want to specify the address of n + m bits of the memory unit 6, first, the upper m bits (An ~~) that cannot be generated in the effective address generator 2 Data for Am + n-1) is written to the mode register 5 by using an input command of the input / output device. Then, the memory processor generates a lower n-bit address Ao to an-1 from the central processing unit 1 to the effective address generator 2 using the memory input / output command. Then, the address decoder 7 decodes the upper m bits (An-Am + n-1) and the lower n-bit addresses (Ao-Aon-1) to address (Ao-Am) having n + m bits. The address of the memory unit 6 is designated by the signal + n-1).

FIG. 3 is a view for explaining the operation of the mode register 5 in detail. When the central processing unit 1 gives a command to write the address data for the upper m bits to the mode register 5 corresponding to the input / output device, The control signal 10W is applied to the clock terminal CLK of the mode register 5 via the control signal bus 30, and at the same time, address data for the upper m bits is transmitted through the data bus 20. Is applied to the input terminal IN and recorded. Subsequently, the address data written in the mode register 5 together with the lower n-bit address signal generated by the effective address generator 2 by the memory address command used is transmitted through the output terminal OUT. 7) is applied.

As described above, according to the addressing system of the present invention, the memory can be increased regardless of the number of address bits of the central processing unit, and the effort and cost of redesigning the existing chip structure can be reduced. It works.

Claims (1)

A valid address generator 2 for receiving an n-bit address signal output from the central processing unit 1 (CPU) and outputting an n-bit address signal, and latching m-bit data output from the central processing unit 1 a mode register 5 for outputting an m-bit signal, an n-bit output signal of the effective address generator 2 and an m-bit output signal of the mode register 5 to decode an n + m-bit address. An address decoder (7) for outputting a signal and a memory section (6) addressed by an output signal of n + m bits of said address decoder (7). Addressing System.