KR970062916A - Memory structure with byte / bit addressing - Google Patents
Memory structure with byte / bit addressing Download PDFInfo
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- KR970062916A KR970062916A KR1019960004932A KR19960004932A KR970062916A KR 970062916 A KR970062916 A KR 970062916A KR 1019960004932 A KR1019960004932 A KR 1019960004932A KR 19960004932 A KR19960004932 A KR 19960004932A KR 970062916 A KR970062916 A KR 970062916A
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Abstract
본 발명은 바이트/비트 어드레싱이 가능한 메모리 구조에 관한 것으로, 종래에는 메모리에 저장되어 있는 바이트 데이터에서 특정 비트의 값만을 읽어낼 경우나 메모리에 저장되어 있는 바이트 데이터에서 특정 비트의 값만을 쓸경우 여러단계의 명령을 수행해야 하는 문제 즉, 비트 데이터 처리를 주된 업무로 하는 경우 여러단계의 명령을 수행해야 하므로 효율성 저하의 문제가 있다. 따라서, 본 발명은 바이트/비트단위로 리드 및 라이트시 필요한 신호들을 구비하도록 하여 바이트(byte)내에 저장되어 있는 데이터의 특정 비트를 처리할 경우 신속하게 논리적으로 처리할 수 있도록 하고, 바이트 단위의 데이터에 대하여 시스템에서 지원하는 대부분의 기능이 비트 단위의 데이터에 대해서도 구현가능하도록 한다.The present invention relates to a memory structure capable of byte / bit addressing. Conventionally, when only a specific bit value is read from byte data stored in a memory, or when only a specific bit value is written in byte data stored in a memory, In other words, when the bit data processing is regarded as the main task, there is a problem of efficiency reduction because it is necessary to execute the instruction of several stages. Accordingly, the present invention provides signals necessary for reading and writing in units of bytes / bits, so that when processing a specific bit of data stored in a byte, it can be processed logically quickly, Most of the functions supported by the system can be implemented for bit-wise data.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제3도는 본 발명 바이트/비트 어드레싱이 가능한 메모리 구조도.Figure 3 is a memory structure capable of byte / bit addressing according to the present invention.
제5도는 비트 단위로 메모리를 리드/라이트할 때의 어드레스 맵.FIG. 5 is an address map when a memory is read / written in units of bits.
제6도는 제3도의 메모리를 적용한 입출력 콘트롤러의 구성도.FIG. 6 is a block diagram of an input / output controller to which the memory of FIG. 3 is applied.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960004932A KR970062916A (en) | 1996-02-27 | 1996-02-27 | Memory structure with byte / bit addressing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960004932A KR970062916A (en) | 1996-02-27 | 1996-02-27 | Memory structure with byte / bit addressing |
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KR970062916A true KR970062916A (en) | 1997-09-12 |
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KR1019960004932A KR970062916A (en) | 1996-02-27 | 1996-02-27 | Memory structure with byte / bit addressing |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190114506A (en) * | 2018-03-30 | 2019-10-10 | 엘에스산전 주식회사 | Programmable logic controller system |
-
1996
- 1996-02-27 KR KR1019960004932A patent/KR970062916A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190114506A (en) * | 2018-03-30 | 2019-10-10 | 엘에스산전 주식회사 | Programmable logic controller system |
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