KR970051199A - Memory read / write circuit - Google Patents

Memory read / write circuit Download PDF

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Publication number
KR970051199A
KR970051199A KR1019950048596A KR19950048596A KR970051199A KR 970051199 A KR970051199 A KR 970051199A KR 1019950048596 A KR1019950048596 A KR 1019950048596A KR 19950048596 A KR19950048596 A KR 19950048596A KR 970051199 A KR970051199 A KR 970051199A
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KR
South Korea
Prior art keywords
memory
read
write circuit
present
address
Prior art date
Application number
KR1019950048596A
Other languages
Korean (ko)
Other versions
KR100215903B1 (en
Inventor
김태훈
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950048596A priority Critical patent/KR100215903B1/en
Publication of KR970051199A publication Critical patent/KR970051199A/en
Application granted granted Critical
Publication of KR100215903B1 publication Critical patent/KR100215903B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Abstract

본 발명의 메모리회로에 관한 것으로서, 특히 램(RAM)에 데이타를 리드(Read) 및 라이트(Write)할 시 램 메모리의 여유공간을 효율적으로 활용할 수 있도록 한 메모리의 리드/라이트회로에 관한 것이다.The present invention relates to a memory circuit of the present invention, and more particularly, to a read / write circuit of a memory capable of efficiently utilizing a free space of a RAM memory when reading and writing data into a RAM.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 메모리의 리드/라이트회로는 일개의 프로그램 카운트값을 받아 복수개의 지정번지값을 출력하는 디코더와, 선택신호에 의해 입력되는 특정비트의 데이타를 상기 디코더의 지정번지값에 대한 홀수번지 및 짝수번지로 분리 선택하고 이 각 번지가 일정 비트를 갖도록 복수개로 분리 선택하는 버스선택부와, 리드 및 라이트 제어신호에 의해 상기 버스선택부에서 분리 선택된 특정 비트 데이타를 저장하거나 내보내는 메모리로 이루어짐을 특징으로 한다.In order to achieve the above object, a read / write circuit of a memory according to an embodiment of the present invention receives a program count value and outputs a plurality of designated address values, and outputs data of a specific bit input by a selection signal. A bus selector for separating and selecting an odd address and an even address for a designated address value of a plurality of bits, and selecting the plurality of bits such that each address has a predetermined bit, and specific bit data selected and separated by the bus selector by read and write control signals. It is characterized by consisting of a memory for storing or exporting.

따라서, 본 발명에 따른 메모리의 리드/라이트회로는 메모리를 효율적으로 운용함으로써 데이타의 전송속도를 향상시키고 메모리의 효율을 향상시키는 효과가 있다.Therefore, the read / write circuit of the memory according to the present invention has the effect of improving the data transfer speed and the memory efficiency by efficiently operating the memory.

Description

메모리의 리드/라이트회로Memory read / write circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 메모리의 리드/라이트회로를 나타낸 구성도.2 is a block diagram showing a read / write circuit of a memory according to the present invention.

Claims (1)

일개의 프로그램 카운트값을 받아 복수개의 지정번지값을 출력하는 디코더와, 선택신호에 의해 입력되는 특정비트의 데이타를 상기 디코더의 지정번지값에 대한 홀수번지 및 짝수번지로 분리 선택하고 이 각 번지가 일정비트를 갖도록 복수개로 분리 선택하는 버스선택부와, 리드 및 라이트 제어신호에 대해 상기 버스선택부에서 분리 선택된 특정 비트 데이타를 저장하거나 내보내는 메모리로 이루어짐을 특징으로 하는 메모리의 리드/라이트 회로.A decoder which receives one program count value and outputs a plurality of designated address values, and separately selects data of a specific bit input by the selection signal into odd and even addresses for the designated address value of the decoder. And a bus selector for separating and selecting a plurality of bits to have a predetermined bit, and a memory for storing or exporting specific bit data separately selected by the bus selector for read and write control signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950048596A 1995-12-12 1995-12-12 Read/write circuit for memory KR100215903B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950048596A KR100215903B1 (en) 1995-12-12 1995-12-12 Read/write circuit for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950048596A KR100215903B1 (en) 1995-12-12 1995-12-12 Read/write circuit for memory

Publications (2)

Publication Number Publication Date
KR970051199A true KR970051199A (en) 1997-07-29
KR100215903B1 KR100215903B1 (en) 1999-08-16

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ID=19439187

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950048596A KR100215903B1 (en) 1995-12-12 1995-12-12 Read/write circuit for memory

Country Status (1)

Country Link
KR (1) KR100215903B1 (en)

Also Published As

Publication number Publication date
KR100215903B1 (en) 1999-08-16

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