JPH06251168A - Address generation circuit for microcomputer incorporating eprom - Google Patents

Abstract

PURPOSE:To provide a microcomputer incorporating an EPROM in which the number of external address terminals can be reduced and with a small number of pins by shoving the high-order of an address in the output of a binary up counter. CONSTITUTION:The address generation circuit of the microcomputer incorporating the EPROM is provided with the EPROM 11, and a binary counter which performs the clock input of the overflow of the low-order addresses A0-An of the EPROM 11 and whose output is connected to the high-order address An+1... of address input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer with a built-in EPROM, and more particularly to an address generation circuit for writing a program.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. FIG. 3 shows such a conventional EPROM built-in OTP (One Time P).
It is a block diagram of a programmable microcomputer.

As shown in this figure, the OTP microcomputer requires power supplies, addresses A _{0 to An} , data D _{0 to} D _n , and control terminals for writing. For example,
If the ROM is 8 kbytes with an 8-bit microcomputer, power supply 3
Book (V _cc , V _pp , GND), Address 13 (8192
= 2 ¹³ ), 8 data, 2 controls (-CE, -OE), and at least 26 terminals were required.

[0004]

However, the above-mentioned conventional microcomputer has a problem that the OTP of the microcomputer having the pin number smaller than 26 pins cannot be performed.
As described above, in order to solve the problem that OTP with a small number of pins cannot be performed, the present invention reduces the number of external address terminals by indicating the upper address by the output of the binary up counter, thereby reducing the number of pins. Number of OT
The purpose is to provide a P microcomputer.

[0005]

In order to achieve the above object, the present invention uses an overflow of an EPROM and a lower address of the EPROM as a clock input in an address generation circuit of an EPROM built-in microcomputer.
A binary counter whose output is connected to the upper address of the address input is provided.

[0006]

According to the present invention, as shown in FIG.
In the address generation circuit of the M built-in microcomputer, EPRO
M11 and the lower address A of this EPROM 11₀~ A
_nOverflow of is used as clock input and output
Is the top A for address input _{n + 1}Binary adapter connected to ...
Since the unta 12 is provided, the number of pins is small.
Microcomputer with built-in EPROM, for example, Myco with less than 24 pins
The built-in EPROM with a large address space
Data can be written.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention E
It is an address generation circuit diagram of a PROM built-in microcomputer. As shown in this figure, the power supply terminal V _pp, the chip enable terminal -CE, out enable terminals -OE, the respective terminals of the address terminals A ₀ to A _n, but each has a function as a microcomputer, the circuit of the microcomputer portion Omitted.

Therefore, the EPROM 11 has a power supply terminal V _pp , a chip enable terminal -CE, an out enable terminal -OE, address terminals A _{0 to An} , and a data terminal D _0.
.., D _n , and address terminals A _{n + 1} to are connected to outputs 0 ₁ , 0 _2, ... Of the binary up counter 12. Further, the clock input of the binary up counter 12 is output to the AND gate 13 and (n
+2) inputs are respectively connected to the address terminals A _{0 to} A _n and the output of the inverter 14, and the input of the inverter 14 is connected to the out enable-OE terminal.

Therefore, when writing sequentially from the address 0 to the EPROM 11, although up to 2 ⁿ can be written in the (n + 1) terminals, the binary up counter 12 can write to a higher address. For example, if the binary up counter 12 has an output of m bits, up to 2 ^{(n + m)} addresses can be indicated. Regarding the input of the reset R, a method of decoding and resetting the address 0000H on the EPROM adapter board, a method of detecting and resetting a high voltage of V _PP , and the like can be considered.

Next, the operation of the address generation circuit of the EPROM built-in microcomputer will be described with reference to FIG. 2 is an operation timing chart of the address generation circuit of the EPROM built-in microcomputer according to the embodiment of the present invention.
2A is a power supply terminal V _PP , FIG. 2B is a reset R, FIG.
(C) the chip enable terminal -CE, FIG. 2 (d) out-enable terminal -OE, FIG 2 (e) ~ (g) are lower address A ₀ to A _n, FIG. 2 (h) the upper address A _{n +1}
(O ₁ ) and FIG. 2 (i) are timing charts of the upper address A _{n + 2} (O ₂ ).

As is apparent from FIG. 2, EPROM 11
When the lower address A ₀ to A _n of overflows, by the rising edge of the out-enable signal (-OE) signal, binary up counter 12 is counted, the output O1, the upper address of O2 ... is EPROM11 A _{n +} 1, A _It is transmitted to _{n + 2} ..., and data can be written up to the upper address.

In this embodiment, however, it is assumed that data is written to the EPROM one address at a time from the lower address to the upper address, and that the same address is not continuously read when reading the data. However, since these depend on the specifications of the EPROM writer, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and these are excluded from the scope of the present invention. Not a thing.

[0013]

As described above in detail, according to the present invention, an address generation having a binary up counter whose overflow is input to the lower address of the EPROM as a clock input and whose output is connected to the upper address of the EPROM. By adding a circuit to a microcomputer with a built-in EPROM, even a microcomputer with a small number of pins, for example, 24 pins or less, can have a built-in EPROM with a large address space and write data.

In this way, by indicating the upper address by the output of the binary up counter, it is possible to reduce the number of external address terminals and provide an OTP microcomputer having a small number of pins.

[Brief description of drawings]

FIG. 1 is an address generation circuit diagram of an EPROM-embedded microcomputer according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the address generation circuit of the EPROM built-in microcomputer according to the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional OTP microcomputer with a built-in EPROM.

[Explanation of symbols]

 11 EPROM 12 Binary up counter 13 AND gate 14 Inverter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Shinozuka 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] 1. An EPROM (a) and an EPROM (b).
And a binary counter whose output is connected to the upper address of the address input, while the overflow of the lower address of the
Address generation circuit for microcomputer with built-in ROM.