JPH06162219A - Write control circuit for microcomputer - Google Patents

Abstract

PURPOSE:To provide the write control circuit of a microcomputer capable of using a general data generating circuit and writing program data into a non-volatile memory in a short time without making a chip area of the microcomputer larger than required. CONSTITUTION:In accordance with a pulse EG generated from an edge detecting circuit 4 at every and fall of the lowest bit A0 of address data, the address data and program data are switched from switching output circuits 11, 12, and outputted in parallel. In such a way, even in the case of the microcomputer in which the number of pins is small, write of the program data to an EPROM 3 can be executed in a short time by using general PROM writer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write control of a microcomputer capable of writing / reading program data and having a small number of derived pins by using a general-purpose PROM writer. Regarding the circuit.

[0002]

2. Description of the Related Art Generally, when writing program data to an EPROM (nonvolatile memory) built in a microcomputer, a data generating circuit called a PROM writer in which address data and program data for that is preset is used. It The data generating circuit generates various outputs to the microcomputer, and has terminals for generating a power supply voltage, a chip enable signal, an output enable signal, address data, program data, and the like. In particular, the address data and the program data described above are output in parallel. If the address data and the program data are m and n bits, respectively, m + n.
A book terminal is required for the data generation circuit. Such a data generating circuit is used as a general-purpose product, but in order to use this data generating circuit, it is necessary to write at least address data and program data unless it is a microcomputer having m + n parallel input pins. There is a problem that the program data cannot be written in the EPROM. Therefore, an EPROM having a smaller number of pins than the number of pins derived from the data generation circuit
When writing program data to the built-in microcomputer, the above-mentioned general-purpose data generating circuit cannot be used, so a dedicated data generating circuit for that purpose is used.

[0003]

The dedicated data generating circuit described above is intended to support a microcomputer having a small number of pins by converting program data from a parallel state to a serial state and outputting the program data. To achieve this, it has a built-in parallel-serial conversion circuit with a relatively large number of elements. Therefore, there is a problem that the cost becomes high to purchase the dedicated data generating circuit. On the other hand, a serial-parallel conversion circuit for returning serially input program data to parallel data must be built in the microcomputer. This conversion circuit has a relatively large number of elements, so if this conversion circuit is built into each microcomputer,
There is a problem that the chip area increases. Further, since the program data is output from the data generating circuit to the microcomputer serially, there is a problem that a lot of time is spent to write the program data in the EPROM.

Therefore, according to the present invention, a general-purpose data generating circuit can be used, and program data can be written in a nonvolatile memory in a short time without increasing the chip area of the microcomputer more than necessary. It is an object of the present invention to provide a write control circuit of.

[0005]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it has a built-in micro-memory capable of writing and reading program data. In a write control circuit of a microcomputer for writing program data to a computer, a data generation circuit for parallelly outputting address data for accessing the nonvolatile memory and program data stored in the nonvolatile memory, the address data, and A switching output circuit for switching and outputting the program data, a pulse is generated by detecting a rising edge and a falling edge of the least significant bit of the address data, and when the pulse is generated, the switching output circuit outputs the address data. , The switching output circuit when the pulse is not generated An edge detection circuit that controls so that the program data is output, and a latch circuit that holds and outputs the address data obtained from the switching output circuit in synchronization with the pulse output of the edge detection circuit. It is a prepared point.

[0006]

According to the present invention, the switching output circuit switches the address data and the program data in parallel according to the pulse generated from the edge detection circuit at every rise and fall of the least significant bit of the address data. Therefore, even a microcomputer with a small number of pins can write program data to the nonvolatile memory in a short time using a general-purpose data generation circuit.

[0007]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a write control circuit of a microcomputer of the present invention. In FIG. 1, (1) is a PROM writer (data generation circuit) for performing a write operation to an EPROM (3) which is built in the microcomputer (2) and capable of writing and reading program data. Address data and program data are preset. Here, EPROM (3) is 1K
Assuming that each address has a byte address and the storage capacity of each address is 8 bits, 10-bit address data A0 to A9 is output from 10 terminals (1A) of the PROM writer (1).
Are output in parallel, and 8-bit program data D0 to D7 are output in parallel from the eight terminals (1B). Further, from the terminals (1C) (1D) (1E) of the PROM writer (1), the EPROM
The chip enable signal * CE which becomes “0” when the (3) is set to the writable state, the output enable signal * OE which becomes “0” when the program data is read from the EPROM (3), and the EPROM (3) The high voltage Vpp applied to the EPROM (3) is output when data is written to the EPROM (3). These outputs are input terminals (2A) (2B) (2C) of the microcomputer (2).
Is applied to the EPROM (3) via. Besides this, P
From the ROM writer (1) to the microcomputer (2)
Although various signals are output for this purpose, they are not related to the present invention, and the description thereof is omitted.

(4) is an edge detection circuit, which generates a detection pulse at every rise and fall of the least significant bit A0 of the address data. As an example of the edge detection circuit (4), there is a circuit shown in FIG. 2, and the waveforms of the respective parts are shown in FIG. That is, three-stage inverter (5)
(6) (7) AND gate (8) for calculating the logical product of the output a of the third inverter and the least significant bit A0 of the address data, NOR for calculating the logical sum of the output a and the least significant bit A0 Gate (9) and outputs b and c
It is composed of an OR gate (10) for calculating the logical sum of the above and generating the detection pulse EG. The number of inverter stages is not limited to three, and may be varied according to the width of the detection pulse EG. For example, if the width of the detection pulse EG is to be increased, the number of inverter stages may be increased to increase the delay of the least significant bit A0. Conversely, if the width of the detection pulse EG is to be shortened, the number of inverter stages may be reduced to the maximum. The delay of the lower bit A0 may be reduced. Further, the edge detection circuit (4) is not limited to that shown in FIG. 2, and may have any configuration as long as it can generate a pulse at the rising and falling edges of the least significant bit A0. Here, the address data changes every time the least significant bit A0 changes to a high level or a low level. Therefore, the detection pulse EG is output at every rising and falling of the least significant bit A0 when the address data changes. The EPROM (3) is generated and the EPROM (3) is accessed at this high-level timing, and the program data to be written to the address is fetched into the EPROM (3) at the next low-level timing.

Reference numeral (11) is a buffer to which 8 bits A0 to A7 excluding the upper 2 bits A8 and A9 of the address data are applied, and eight buffers are provided corresponding to each bit.
Further, (12) is 8-bit program data D0 to D7.
Is a transmission gate to which is applied, and eight are provided corresponding to each bit. The buffer (11) and the transmission gate (12) form a switching output circuit, and each is controlled by the detection pulse EG of the edge detection circuit (4). That is, when the detection pulse EG is at high level, the buffer (11) outputs the address data A0 to A7, and when the detection pulse EG is at low level, the transmission gate (12) outputs the program data D0 to D7. Is output. The 8-bit data switched and output from the buffer (11) and the transmission gate (12) is taken into the microcomputer (2) via the terminal (2D).

(13) is a latch circuit, which has terminals (2
The address data A0 to A7 of 8 bits is held when triggered by the detection pulse EG taken into the microcomputer (2) via E), and 8 pieces are provided corresponding to each bit. . Then, the 8-bit address data A0 output from the latch circuit (13)
˜A7 and the upper 2 bits A of the address data taken into the microcomputer (2) via the terminal (2F)
8 and A9 are simultaneously applied to the EPROM (3) so that the E
The PROM (3) is accessed. On the other hand, the terminal (2
The program data fetched by D) is not stored in the latch circuit (13) and is directly stored in the EPROM.
It is written to the address being accessed by being applied to (3).

According to the above configuration, since the terminal (2D) for taking in 8 bits of the address data and the program data in parallel to the microcomputer (2) is shared, the eight terminals are independently connected to the microcomputer. It is not necessary to provide it on the CPU and is effective for a microcomputer having a small number of terminal pins. A general-purpose PROM that outputs address data and program data independently in parallel
The writer (1) can be used in a microcomputer having a small number of terminal pins, and it is not necessary to use a dedicated PROM writer as in the conventional case, and the cost therefor can be suppressed. Further, since the address data and the program data can be transmitted in parallel from the PROM writer (1) to the microcomputer (2), the writing time of the program data to the EPROM incorporated in the microcomputer having a small number of terminal pins can be shortened as compared with the conventional case. it can.
Further, only a latch circuit having a relatively small number of elements is arranged on the chip of the microcomputer (2), and the remaining edge detection circuit and switching output circuit are provided on a substrate outside the microcomputer (2). . Here, the microcomputer (2) described above produces a relatively large number, but the number of substrates produced is very limited. Therefore, since it is equivalent to producing only the microcomputer (2), it is possible to suppress an increase in the chip area and thereby suppress an increase in cost.

[0012]

According to the present invention, since the address data and the program data are switched and output in parallel, the terminals of the microcomputer for fetching both data can be shared, which is effective for a microcomputer having a small number of terminal pins. In addition, a general-purpose data generation circuit that outputs address data and program data independently in parallel can be used in a microcomputer with a small number of terminal pins, eliminating the need to use a dedicated data generation circuit as in the past, thus reducing the cost. Can be suppressed. Further, since the address data and the program data can be transmitted in parallel from the data generating circuit to the microcomputer, the writing time of the program data to the nonvolatile memory built in the microcomputer having a small number of terminal pins can be shortened as compared with the conventional case. Further, only a latch circuit having a relatively small number of elements is arranged on the chip of the microcomputer, and the remaining edge detection circuit and switching output circuit are provided on a substrate outside the microcomputer. Here, although the above-mentioned microcomputer produces a relatively large number, the above-mentioned number of substrates produced is very limited. Therefore, since it is equivalent to producing only a microcomputer, it is possible to obtain advantages such as suppressing an increase in the chip area and suppressing an increase in cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a write control circuit of a microcomputer of the present invention.

FIG. 2 is a diagram showing an embodiment of an edge detection circuit used in FIG.

FIG. 3 is a waveform diagram showing waveforms at various points in FIG.

[Explanation of symbols]

 (1) PROM writer (2) Microcomputer (3) EPROM (4) Edge detection circuit (11) Buffer (12) Transmission gate (13) Latch circuit

Claims (2)

[Claims] 1. A write control circuit of a microcomputer for writing program data to a microcomputer having a built-in nonvolatile memory capable of writing and reading program data, comprising: address data for accessing the nonvolatile memory; Generating circuit for parallelly outputting the program data stored in the volatile memory, a switching output circuit for switching the address data and the program data and outputting in parallel, and detecting a rising edge and a falling edge of the least significant bit of the address data. To generate a pulse, and the address data is output from the switching output circuit when the pulse is generated,
An edge detection circuit that controls the program data to be output from the switching output circuit when the pulse is not generated; and the address data obtained from the switching output circuit in synchronization with the pulse output of the edge detection circuit. A latch circuit that holds and outputs the program data output from the switching output circuit to the accessed address by accessing the nonvolatile memory with the address data held in the latch circuit. And a write control circuit for a microcomputer. 2. The microcomputer according to claim 1, wherein the edge detection circuit and the switching output circuit are provided on a substrate outside a microcomputer, and the latch circuit is provided inside the microcomputer. Embedded control circuit.