JPH0369089A - Memory - Google Patents

Abstract

PURPOSE:To improve efficiency for an access by adding a circuit to continuously generate addresses in a memory. CONSTITUTION:When the discontinuous address is accessed, namely, in the case of the normal access, an address 100 to be sent out of an address buffer 1 in the order of a row address and a column address is decoded as it is by a row decoder 3 and a column decoder 5 and applied to a memory cell array 6 and data are written or read. On the other hand, when the continuous address is accessed, by the first access, the row address and column address are respectively latched to address latch/increment circuits 21 and 22. After a second access, by inputting an inverted SA signal 9 to an address increment circuit 4, the previously accessed address is increased, outputted from the circuits 21 and 22 and decoded by decoders 3 and 5. Then, the address is determined.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to memories, and more particularly to
The present invention relates to a memory including a storage circuit that allows data to be read and written to an address by specifying one address.

Prior Art In general, this type of memory is DRAM (Dy
naslc RAM). Conventionally, DRAMs have the same row address and column address input pins. Therefore, in order to determine the address to be accessed, it was necessary to shift the input timing of the row address and column address.

In this case, RA S (Row Address 5L
robc) and CAS (Column Address
The address was specified by inputting ``5trobe'' and ``5trobe'' at different timings.

However, the above-mentioned conventional DRAM has the disadvantage that even when accessing consecutive addresses, a row address and a column address must be input each time the access is made, resulting in poor access efficiency.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a memory that can improve access efficiency.

Structure of the Invention The memory according to the present invention is a memory that includes a storage circuit that allows data to be read and written to one of the consecutive addresses by specifying the address, and the memory is a memory that includes a memory circuit that allows data to be read and written to one of consecutive addresses, and that does not require input of an initial address from the outside. and an address generation circuit that sequentially generates the next address from the initial address in response to input of a continuous read command, and the address generated by this address generation circuit is used as a specified address for the storage circuit. It is characterized by

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. tri1 is a block diagram showing the configuration of one embodiment of the memory according to the present invention. In the figure, a memory according to an embodiment of the present invention includes a RAS control circuit 10 and a CAS control circuit 1.
2, an address buffer 1, address latch/increment circuits 21 and 22, an address increment control circuit 4, a row decoder 3, a column decoder 5, a memory cell array 6, and an I10 switch buffer 7. ing. In addition, 9 is S A (Ser
ial^ddrcss (continuous access) signal, and by inputting this signal, addresses are generated in sequence in the memory.

The address increment control circuit 4 is
Address latch/increment circuit 2 according to A-fold signal
1 and 22.

are taken in and given to the address buffer 1 in order.

Address buffer 1 is for responding to the falling edge of RAS II and CAS 13 to send out address 8 from a host device such as a CPU.

The row decoder 3 decodes the row address 210 from the address latch/increment circuit 21 and provides it to the memory cell array 6.

Column decoder 5 decodes column address 22G from address latch/increment circuit 22 and provides it to memory cell array 6.

The memory cell array 6 is a storage area in which data can be read and written to cells corresponding to addresses given by the row decoder 3 and column decoder 5.

The I10 switch buffer 7 performs a switching operation in response to a write operation or a read operation to the memory cell array 6, and writes or reads data 70.

Next, using FIG. 4, address increment control circuit 4 and address latch/increment circuit 2 in FIG.
1 will be explained.

FIG. 4 is a detailed diagram of the address increment control circuit 4 and the address latch/increment circuit 21, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. In addition,
It is assumed that the address latch/increment circuit 22 in the figure has substantially the same internal configuration as the address latch/increment circuit 21.

In the figure, address latch/increment circuit 21
are buffers 211 and 212, an inverter 213,
The counter 214 is configured to include a counter 214.

The second buffer 212 and the inverter 213 operate the address buffer 1 (
1), or the address 215 from the counter 214.

That is, the logic level of the external address valid signal 41 is 0.
”, the buffer 211 is enabled and the address 10
0 is sent as is as the row address 210, and when the logic level is "1", the buffer 2!2 is enabled and the address 215 from the counter 214 is sent as the row address 210.
It is sent as 0.

The counter 214 has a function of capturing and presetting 10 addresses when the address preset signal 42 is valid, and responds to the rising timing of the address increment signal 43 input to the clock input terminal CLK. It performs a counter operation. That is, in the counter operation of this counter 214, the address 215 that is incremented by 1! is the row address 21.
It is sent out as 0.

That is, when accessing consecutive addresses, the address is preset in the counter 214 during the first access, and the address is incremented in accordance with the counting operation during the second and subsequent accesses.

Also, normally only the row address is incremented.

In other words, only the counter 214 in the address latch/increment circuit 21 performs a counting operation, and the counter (not shown) in the address latch/increment circuit 22 does not perform a counting operation.

However, when the counter 214 overflows and the carry signal 44 is sent out, a counter (not shown) in the address latch/increment circuit 22 performs a counting operation in accordance with the control signal 40 from the address increment control circuit 4 at that timing. As a result, the column address will also be incremented. Note that the control signal 40 is a signal equivalent to the external address valid signal 41, address preset signal 42, and address increment signal 43.

In other words, address latch/increment circuit 21.2
A row address and a column address can be preset in each of the counters in the counter 2, and by subsequently inputting an SA scratch signal, the row address and column address are incremented and data is written or read.

Returning to FIG. 1, in the memory with such a groove bottom,
When accessing non-consecutive addresses, that is, in the case of normal access, the address 100 is sent from address buffer 1 in the order of row address and column address.
is decoded as is by the row decoder 3 and column decoder 5, and is applied to the memory cell array 6, where data is written or read.

On the other hand, when accessing consecutive addresses, the row address and column address are respectively latched by the address latch/increment circuits 21 and 22 at the first (first) access. Then, in the second and subsequent accesses, by inputting the SA signal 9 to the address increment control circuit 4, the address latch/increment circuit 2 outputs an address obtained by incrementing the previously accessed address. Furthermore, the address to be accessed is determined by being decoded by the row decoder 3 and column decoder 5, respectively. Note that a configuration may be adopted in which the number of addresses is decreased instead of increased.

Furthermore, the operation of the memory shown in FIG. 1 will be explained using FIGS. 2 and 3. FIG. 2 is a timing chart at the time of the first access when consecutive addresses are accessed. First, the row address is latched at the falling edge of RAS, and the column address is latched at the falling edge of CAS. In this way, the address to be accessed is determined, and a write or successive write operation is performed.

Further, FIG. 3 is a timing chart for the second and subsequent accesses when accessing by consecutive addresses. From the second time onward, the address that is incremented from the previously accessed address is latched at the falling edge of SA. Thus, a new address is determined and a write or read operation is performed.

In this way, in this embodiment, since a circuit for incrementing addresses is provided in the DRAM, access efficiency can be improved and high-speed access becomes possible.

In addition, in this embodiment, the case where the memory is DRAM was explained, but SRAM (StaLi
It is clear that the present invention can also be applied to ORAM.

However, current SRAM has independent row address and column address input bins, and there is no need to shift the timing of address input unlike DRAM.
Access efficiency remains unchanged. However, it has the effect of eliminating the need to send an address from a host device such as a CPU.

As described in detail, the present invention adds a circuit that continuously generates addresses in the memory, thereby eliminating the need to input addresses from the second time onwards when accessing consecutive addresses. This has the effect of shortening the access time and improving access efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of a memory according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts showing the operation of the memory in FIG. 1, and FIG. 4 is an address latch in FIG. 1. It is a detailed diagram centered on the increment Ijl path. Explanation of the symbols of the main parts 1...Address buffer

Claims (1)

[Claims] (1) A memory that includes a memory circuit that allows data to be read and written to one of the consecutive addresses by specifying that address, and after inputting an initial address from the outside, a continuous read command is issued. 1. A memory comprising: an address generation circuit that sequentially generates the next address from the initial address in response to an input of the address, and the address generated by the address generation circuit is used as a designated address to the storage circuit.