JP2002208289A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can be operated at a high speed, while in which output can be performed with several kinds of the number of bits, operation speed can be increased by decreasing the number of output bits. SOLUTION: A single bank output section (x bits) 3 is divided into (n) parts and interleave access is performed, while plural interleave access circuit means 4 in which output can be performed from the bank output section with several kinds of the number of bits is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which is an electrically rewritable nonvolatile memory, and more particularly to a semiconductor memory device which changes output data to reduce a read time.

[0002]

2. Description of the Related Art A flash memory is an electrically rewritable non-volatile memory, and is one of the most effective memories as a storage butterfly of a semiconductor file storage device because of its large capacity and low cost. , Conventional EPROM and EE
It is widely used as an element for replacing a PROM and for storing a file. In particular, recently, with the advancement of functions in the field of portable electronic devices (digital circuit devices), high-speed operations of mounted flash memories are required.

A flash memory is a memory that performs read access by determining the presence / absence of a current in a memory cell. The higher the memory cell current, the higher the speed of operation. Generally, since the threshold voltage of a memory cell is 1.5 V or more, it is not possible to secure a memory cell current in a low voltage region, and it is very difficult to speed up read access. To solve this problem, several circuit technologies such as threshold voltage control and word line boosting have been devised.

However, the conventional word line boosting circuit has a problem in that the memory cell current is reduced due to a decrease in the word line potential in a low voltage region and the access time is deteriorated because the power supply voltage largely depends. Further, in the high voltage region, the word line potential rises, and thus there is a problem of reliability peculiar to flash EEPROM such as gate disturb.

Since the read cycle of the flash memory has a limit, the memory cell is divided into an even bank and an odd bank for high-speed operation, and the operating frequency is changed by an interleave architecture in which each bank is accessed alternately. There is a way to raise it. Hereinafter, this will be described as a conventional example.

A flash memory using an interleave architecture divides a memory cell into an even-numbered bank and an odd-numbered bank and alternately accesses each bank, thereby performing a high-speed operation twice as long as a cycle for reading out a memory cell. Is the way. As an example of this, `` 1.4V60MHz
Access 0.25um Built-in Flash EEPROM "(IEICE Technical Report, lCD99-33, 1999-05).

FIG. 21 is a block diagram of a flash memory using an interleave architecture. Also,
FIG. 22 is a timing chart of the flash memory using the interleave architecture.

As shown in FIG. 21, the flash memory comprises a control circuit 101, an address latch 102, an odd-numbered memory cell 103, an even-numbered memory cell 104, latches 105-1 and 105-2, and a multiplexer 106. Is done.

In this configuration, in order to increase the maximum operating frequency, the memory cells of the flash memory are stored in even-numbered banks 104.
And the odd-numbered bank 103. Then, in synchronization with the rising edge of the clock for outputting the address A (1), the odd-numbered bank 103 performs address latching / decoding, and thereafter, the bit line is recharged through a reset operation.

Next, in synchronization with the rise of the clock for outputting the address A (2), in the odd-numbered bank 103, sensing and operation of the memory cell current and driving of the data bus are performed, and the sense amplifier starts current sensing. I do. At this time,
In the even-numbered bank 104, address latch decoding is performed, and thereafter, bit lines are recharged via a reset operation.

As described above, the even-numbered bank 104 and the odd-numbered bank 103 alternately perform read access, output data, and input the data to the latch. Data latched by the latches 105-1 and 105-2 from the even-numbered bank 104 and the odd-numbered bank 103 are alternately selected by the multiplexer (MUX) 106 and output to the output terminal d_out.

As described above, the interleave access is realized, and the operating frequency can be twice as long as the cycle for reading the memory cell.

[0013]

In the conventional flash memory, each memory cell is divided into an even bank and an odd bank, and the even bank and the odd bank are alternately accessed by employing an interleave architecture. The operation can be performed at a speed higher than the operation speed for accessing the bank. However, in the two-bank configuration, the operation at double speed for each bank access is limited. In addition, since the memory cells are divided into banks, only certain fixed bits can be output. When changing the output bits of the flash memory in the conventional interleaved architecture, it is necessary to reconfigure the bank division, which is flexible. Lack of sex.

It is an object of the present invention to provide a semiconductor memory device which can operate at high speed, can output with several kinds of bits, and can increase the operation speed by reducing the number of output bits. With the goal.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor memory device having electrically rewritable nonvolatile memory cells. Control means for outputting a clock signal and controlling access to the memory cell; access means for decoding the address to access the memory cell; and a plurality of interleave access circuits corresponding to data of several types of bits And an output switching means for changing the number of bits of output data of the flash memory by switching the circuit.

According to a second aspect of the present invention, in the first aspect of the present invention, the output switching means changes the operation speed by switching the interleave access circuit.

According to a third aspect of the present invention, in the first aspect of the present invention, the output switching means includes at least a plurality of latches.

According to a fourth aspect of the present invention, in the first aspect, the output switching means includes at least a plurality of latches and a plurality of multiplexers.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a circuit to which the present invention is applied, and FIG. 2 is a timing chart showing the operation of the circuit shown in FIG.

As shown in FIG. 1, a circuit to which the present invention is applied includes a control circuit 1, an address latch 2, a memory cell output section 3, and an output section switching circuit 4.

_CE (_CE is _CE = 'L' and Tu
re) and the clock signal mclk × n. mclk × n is
This is a clock signal when the output of the memory cell is divided by n and read at an operation speed n times as large as mclk. The control circuit 1 has a built-in counter circuit for dividing mclk × n.
Can be ^divided by 1/2 ⁿ . The divided clock signal is
It is input to the output switching circuit 4. _CE output from the control circuit 1 becomes 'L', and the address is latched. Here, it is assumed that the address A (1) is latched. Next, x-bit data corresponding to the address A (1) is output with the read clock mclk of the memory cell D (1). D (1) passes through the output switching circuit 4 and is interleaved at an operating speed of mclk × n, and outputs x / n-bit data D (1_1) to D (1_N).

[0023]

Next, in the semiconductor memory device according to the present invention, the memory cell output section is divided and a plurality of interleave access circuits are provided, so that it is possible to output from the flash memory with several kinds of bits. There are two embodiments for improving the operation speed by reducing the number of output bits of the first embodiment, and the first and second embodiments will be described below.

[First Embodiment] FIG. 3 is a diagram showing a circuit including the configuration of the output section switching circuit 4. As shown in the figure, the output section switching circuit 4 includes a latch 41 and a latch 42 (4
2-1 to 42-3), latch 43 (43-1 to 43-)
7), a multiplexer 44 (44-1 to 44-4) for performing interleave access, and a multiplexer 45 for selecting the number of output bits of the flash memory. And mclk × n signals that control them.

FIG. 4 is a diagram showing the configuration of the latch 41, FIG. 5 is a diagram showing the configuration of the latch 42, and FIG. 6 is a diagram showing the configuration of the latch 43.

The operation when the output bit of the flash memory is changed will be described below.

(1) The flash memory output is 32 bits,
Description of Operation Speed of mclk FIG. 7 is a diagram showing a data flow when the flash memory output is 32 bits and the operation speed is mclk, and FIG. 8 is a timing chart thereof.

In FIG. 7, 32-bit data f (31: 0) output from the memory cell output unit 3 indicated by a solid line is latched by the latch 41 at mclk. The latched data m_1_Out is output by setting m_div to '0', and the output of the flash memory can be operated by 32 bits, mclk.

(2) The flash memory output is 16 bits,
Description of Operation Speed of mclk × 2 FIG. 9 is a diagram showing a data flow when the flash memory output is 16 bits and the operation speed is mclk × 2, and FIG. 10 is a timing chart thereof. .

In FIG. 9, the 32-bit data output from the memory cell output unit 3 is represented by f (3
1:16) and f (15: 0).
-1, 42-2. Data m after latch (31: 1
5) and m (15: 0) are multiplexed to the multiplexer 44-1 by mclk '0' and '1'. The multiplexed data m_2_out_s is latched by the latch 42-3 at mclk × 2, and the latched data m_2_out is output by setting m_div to “1”. It can be operated twice.

(3) Description of the case where the flash memory output is 8 bits and the operation speed is mclk × 4 FIG. 11 shows the data flow when the flash memory output is 8 bits and the operation speed is mclk × 4. FIG. 12 is a timing chart.

In FIG. 11, the 32-bit data output from the memory cell output unit 3 is expressed by f
(31:24), f (24:16), f (15: 8), and f (7: 0), and each is divided into latches 43-1, 43-2, 43-3,
Input to 43-4. Latched data m (31:24), m (2
4:16), m (15: 8) and m (7: 0) are multiplexed by multiplexers 44-2 and 44-3 by mclk '0' and '1'. Multiplexed data m_4_1_out_s and m_4
_2_out_s are mclk × 2 and latches 43-5 and 43
The latched data m_4_1_out and m_4-_
2_out is further multiplexed into the multiplexer 44-4 by mclk × 2 '0' and '1'. The multiplexed data m_4_out_s is latched by the latch 43-7 with mclk × 4, and the latched data m_4_out is obtained by setting m_div to “2”.
And the output of the flash memory can be operated with 8 bits and 4 times of mclk.

FIG. 1 shows the horizontal structure when the output of the flash memory is 8 bits and the operation speed is mclk × 4.
3 may be used.

[Second Embodiment] FIG. 14 is a diagram showing a configuration of an output section switching circuit 4 in a second embodiment. As shown in the figure, the output section switching circuit 4 includes switches sO to S31 and a matrix switch 4 for performing interleave access.
6. A demultiplexer 47 (47-0 to 47-31) for switching the number of output bits of the flash memory, and a multiplexer (not shown) for selecting the number of output bits of the flash memory.

F (31: 0) output data from the memory cell, do
ut (31: 0) is the output data section of the flash memory. A
(0) to A (3) are mclk as '00', '01', '10', '11'
Access sequentially at × 4 operation speed. So '00', '0
One cycle to read 1 ',' 10 ',' 11 'and A (0) to A (3)
Equivalent to the cycle of reading memory cells with mclk. Therefore, the data output from the memory cell is maintained during the period of A (0) to A (3).

The matrix switch 46 has a switch at the intersection, and generates a control signal for turning on sO-s31. The number of divisions of the output bits of the flash memory is determined by the demultiplexer 47.

The operation when the output bit of the flash memory is changed will be described below.

(1) The flash memory output is 32 bits,
Description when the operation speed is mclk FIG. 15 is a diagram showing the configuration of the matrix switch when the flash memory output is 32 bits and the operation speed is mclk. FIG. 16 is a timing chart at this time.

Here, m_Address represents an address of a memory accessed by mclk. By setting all the matrix switches to “ON”, sO to s31 in FIG. 14 are always “ON” in all the periods A (0) to A (3). This allows
32-bit data f1 (3
1: 0) is a period of A (0) to A (3) through the demultiplexer 47 selected as '0', and 32 bits of data f1 (31: 0) are stored in dout (31: 0). Output. In the next period A (0) to A (3), the next 32-bit data f2 (31: 0) is read from the memory cell.
Is read, and f2 (31: 0) is output to dout (31: 0).

(2) The flash memory output is 16 bits,
Description when Operation Speed is mclk × 2 FIG. 17 is a diagram showing a configuration of a matrix switch when the flash memory output is 16 bits and the operation speed is mclk × 2. FIG. 18 is a timing chart at this time.

In A (0) and A (1), g_sO to g_s15 are set to “ON” so that sO to s15 are set to “ON”. S16-s3 for A (2), A (3)
G_s16 to g_s31 are set to “ON” so that 1 is set to “ON”.

As a result, during the periods A (0) and A (1), the lower 16-bit data f1 (15: 0) of the memory cell passes through the demultiplexer 47 selected as '1' and outputs dout (15). : 0).

Next, during the periods of A (2) and A (3), the upper 16-bit data f1 (31:16) of the memory cell passes through the demultiplexer 47 selected as '1', and the data dout (31). : 16)

As a result, the output of the flash memory can be operated at 16 bits and the read speed is mclk × 2, while the output of the memory cell is 32 bits and the read speed is mclk.

(3) Description of the case where the flash memory output is 8 bits and the operation speed is mclk × 4 FIG. 19 shows the configuration of the matrix switch when the flash memory output is 8 bits and the operation speed is mclk × 4. FIG. FIG. 20 is a timing chart at this time.

In A (0), g_sO ~ is set so that sO ~ s7 become 'ON'.
g_s7 is set to 'ON'. In A (1), g_s8 to g_s15 are set to “ON” so that s8 to s15 are set to “ON”. In A (2), s16-s23 are 'ON'
G_s16 to g_s23 are set to 'ON' so that A (3) for s24
G_s24 to g_s31 are set to 'ON' so that ~ s31 is set to 'ON'.

As a result, during the period of A (0), the lower 8 bits of data f11 (7: 0) of the memory cell are output as dout (7: 0) through the demultiplexer 47 selected as “2”. I do. In the period of A (1), 9-16-bit data f1 (15: 8) from the bottom of the memory cell is output as dout (15: 8) through the demultiplexer 47 selected as '2'. Next, A
In the period (2), the data f1 (23:16) of 17-24 bits from the lower order of the memory cell is output as dout (23:16) through the demultiplexer 47 selected as '2'. In the period of A (3), the upper 8 bits of data f1 (31: 2
4) is passed through the demultiplexer 47 selected as '2'
Output as t (31:24).

Thus, the output of the flash memory can be operated at 8 bits and the read speed is mclk × 4, while the output of the memory cell is 32 bits and the read speed is mclk.

[0049]

As described above, according to the present invention, a single bank output section (x bits) is divided into n parts and interleaved access is performed, so that x / n bits, mc
High-speed operation of n times lk can be performed.

Also, since there are provided a plurality of interleave access circuit means capable of outputting from the bank output section with several kinds of bits, it is possible to output from the flash memory with several kinds of bits and to reduce the number of output bits. The operation speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit to which the present invention is applied.

FIG. 2 is a timing chart showing the operation of the circuit shown in FIG.

FIG. 3 is a diagram showing a circuit including a configuration of an output unit switching circuit 4.

FIG. 4 is a diagram showing a configuration of a latch 41;

FIG. 5 is a diagram showing a configuration of a latch 42;

FIG. 6 is a diagram showing a configuration of a latch 43;

FIG. 7 is a diagram showing the flow of data when the flash memory output is 32 bits and the operation speed is mclk.

FIG. 8 is a timing chart when the flash memory output is 32 bits and the operation speed is mclk.

FIG. 9 is a diagram showing a data flow when the flash memory output is 16 bits and the operation speed is mclk × 2.

FIG. 10 is a timing chart when the flash memory output is 16 bits and the operation speed is mclk × 2.

FIG. 11 is a diagram showing a data flow when the flash memory output is 8 bits and the operation speed is mclk × 4.

FIG. 12 is a timing chart when the flash memory output is 8 bits and the operation speed is mclk × 4.

FIG. 13 is a diagram showing another configuration when the flash memory output is 8 bits and the operation speed is mclk × 4.

FIG. 14 is a diagram illustrating a configuration of an output unit switching circuit 4 according to the second embodiment.

FIG. 15 is a diagram showing a configuration of a matrix switch when a flash memory output is 32 bits and an operation speed is mclk.

FIG. 16 is a timing chart when the flash memory output is 32 bits and the operation speed is mclk.

FIG. 17 is a diagram showing a configuration of a matrix switch when the flash memory output is 16 bits and the operation speed is mclk × 2.

FIG. 18 is a timing chart when the flash memory output is 16 bits and the operation speed is mclk × 2.

FIG. 19 is a diagram showing a configuration of a matrix switch when the flash memory output is 8 bits and the operation speed is mclk × 4.

FIG. 20 is a timing chart when the flash memory output is 8 bits and the operation speed is mclk × 4.

FIG. 21 is a block diagram of a flash memory using a conventional interleave architecture.

FIG. 22 is a timing chart of a flash memory using a conventional interleave architecture.

[Explanation of symbols]

 Reference Signs List 1 control circuit 2 address latch 3 memory cell output unit 4 output unit switching circuit 41 latch 42-1 to 42-3 latch 43-1 to 44-7 latch 44-1 to 44-4 multiplexer 45 multiplexer 46 matrix switch 47-0 ~ 47-31 Demultiplexer s0 ~ s31 switch

Claims (4)

[Claims] 1. A semiconductor memory device having electrically rewritable nonvolatile memory cells, wherein a clock signal is frequency-divided to output a plurality of clock signals,
Control means for controlling access to the memory cell; access means for decoding the address to access the memory cell; and a plurality of interleave access circuits respectively corresponding to data of several types of bits. And an output switching means for changing the number of bits of output data of the flash memory by switching the data. 2. The semiconductor memory device according to claim 1, wherein said output switching means changes an operation speed by switching said interleave access circuit. 3. The semiconductor memory device according to claim 1, wherein said output switching means includes at least a plurality of latches. 4. The semiconductor memory device according to claim 1, wherein said output switching means includes at least a plurality of latches and a plurality of multiplexers.