JPS61167982A - Memory integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to memory integrated circuits.

(Prior Art) Whether data read from a memory integrated circuit is output in parallel or in series, the reading must be controlled so that it is in the order of intended use.

For example, data for CRT display must be retrieved from the memory integrated circuit in the CRT scanning order, and data for printer output must be retrieved from the memory integrated circuit in the printer scanning order. Taking the ROM for character generator memory as an example, there are generally two types of ROM: row scan method and column scan method, and the data is stored in the order in which one character's worth of data is stored horizontally or vertically. Since the data is stored in divided form, it is necessary to use different ROMs depending on the purpose.

Furthermore, a memory integrated circuit has been proposed which has a memory circuit configured such that both the row scan method and column scan method can be shared by the same ROM by using a display method selection signal and an additional circuit.

A conventional memory integrated circuit having this configuration is shown in FIG.

In the figure, 1 is an address input signal, 2 is a display method selection signal, 3 is a data output signal, 4 is an address decoding circuit,
5 is a memory cell group, and 6 is a data selection circuit. In response to inputting the display method selection signal 2 to the data selection circuit 6 from the outside at a high level or a low level, the data read out from the memory cell group 5 by the row scan method or column scan method is changed to data. It is output as output signal 3.

(Problems to be Solved by the Invention) The conventional memory integrated circuit described above has the drawback that it is necessary to input a display method selection signal from the outside and the number of terminals increases.

The present invention eliminates such drawbacks and provides a memory integrated circuit in which the output format of data corresponding to the display method can be selected by inputting a specific address.

(Means for Solving the Problems) A memory integrated circuit of the present invention includes a memory cell group, a data selection circuit that makes the output format of a data output signal from the memory cell group variable, and an address of the memory cell group. and selecting means for comparing an address input signal specifying a specific address with a specific address to control the data selection circuit and select an output format of the data output signal.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of a ROM which is an embodiment of the present invention. 1 is an address input signal, 2 is a display method selection signal,
3 is a data output signal, 4 is an address decode circuit, 5 is a memory cell group, 6 is a data selection circuit, 7 is a fixed address generation circuit, 8 is a comparison circuit, 9 is a coincidence detection signal, 10 is a display method selection signal generation circuit It is. Comparator 8 compares the output of fixed address generation circuit 7 and address input signal 1, and when both match, makes match detection signal 9 active. This activated coincidence detection signal 9 inverts the state of the display method selection signal generation circuit 10. The tab display method selection signal 2 is inverted to switch the data output format from the row scan method to the column scan method or vice versa.

Therefore, the data output format can be selected simply by accessing a specific address using the address input signal 1. Regarding the setting of this specific address, in the case of a character generator ROM like this example,
Generally, a ROM for a character generator has an undefined area, so an unused address can be used to set a specific address.

Furthermore, even when the present invention is applied to something other than a ROM for a character generator, since the specific address is a very small part of the capacity of the memory integrated circuit, the use of this specific area should be avoided during design. is easy.

(Effects of the Invention) As described above, the present invention has the advantage that the data output format can be selected simply by accessing a specific address without adding any terminals or external hardware.

Furthermore, when the present invention is applied to a ROM for a character generator, it is possible to use the row scan method without adding any terminals.
RO with the same content for both column scan methods
You can share M. Therefore.

The number of ROM types that were manufactured in both formats has been halved, which has a significant impact on cost reduction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory integrated circuit. 1°... Address input signal, 2... Display method selection signal, 3... Data output signal, 4...
...address decoding circuit, 5...memory cell group, 6...interval data selection circuit, 7...fixed address generation circuit, 8...music comparison circuit, 9... ...
Coincidence detection signal, 10... Display method selection signal generation circuit.

Claims (1)

[Claims] A memory cell group, a data selection circuit that makes the output format of a data output signal from the memory cell group variable, and a data selection circuit that compares an address input signal that specifies an address of the memory cell group with a specific address. and selecting means for controlling and selecting an output format of the data output signal.