JPH02281347A - Clock generator - Google Patents

Abstract

PURPOSE:To operate a system more surely by providing a clock generator with a ready signal generating circuit to give the function which outputs a multiword signal capable of coping with even a DRAM nibble mode. CONSTITUTION:A clock generator 2 incorporates a ready signal generating circuit 21 which generates a ready signal used for a microprocessor. The circuit 21 outputs plural signals for transfer data indicating that effective data is outputted to an external device at the time of read of the processor 3 and that the external device takes in data at the time of write. At this time, a wait control signal is outputted to the generator 2, and the circuit 21 generates a ready signal after inserting a required wait cycle. Thus, the circuit 21 has the function which outputs the multiword signal capable of coping with the DRAM nibble mode, and the system is operated more surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generator that generates a ready signal in a system using a microprocessor.

[Conventional technology]

FIG. 3 shows an example of a system configuration using a conventional clock generator. In the figure, 1 is an address decoder/controller, 2 is a clock generator (CG), 3 is a microprocessor (MPU), and 4 is an address decoder/controller.
5 is a DRAM nibble mode ready signal generation circuit, and 5 is a selection circuit for outputting a ready signal from either the clock generator 2 or the DRAM nibble mode ready signal generation circuit 4 to the microprocessor 3.

Next, the operation will be explained. Here, when the address of the device to be accessed by the microprocessor 3 is input to the address decoder/controller 1, the wait number information of the device to be accessed is
is output to the clock generator 2 and the DRAM nibble mode ready signal generation circuit 4. The clock generator 2 and the DRAM nibble mode ready signal generation circuit 4 use the wait number information WAITAO-
□ After inserting a wait cycle according to , output a ready signal. As a result, each ready signal is input to the selection circuit 50, and any selected ready signal (READY) is sent to the microprocessor 3 by the control signal (WORD) output from the address decoder/controller 1. It will be output. In this case, when the clock generator 2 is selected, a ready signal for 1 word is output, and when the DRAM nibble mode ready signal generation circuit 4 is selected, a ready signal for 4 words is output.

[Problem to be solved by the invention]

However, since the conventional clock generator is configured as described above, a DRAM nibble mode ready signal generation circuit 4 is required in addition to the ready signal generation circuit in the clock generator 2, so that the clock generation source is The advantage of being able to output a synchronized ready signal within the clock generator 2 cannot be obtained, and there is a problem in terms of reliability of system operation.

The present invention is designed to solve the above-mentioned problems, and includes a DRAM nibble in the clock generator.
The clock generator has the function of outputting multiple words of ready signals that can be used with multiple words, and also outputs ready signals that are synchronized with the clock generation source, increasing the reliability of system operation. The purpose is to obtain.

[Means to solve the problem]

A clock generator according to the present invention incorporates a circuit that generates ready signals corresponding to a plurality of words.

[Effect]

In the present invention, ready signals for multiple words can be synchronized and generated within the clock generator in the case of DRAM nibble mode, etc., thereby increasing the reliability of system operation.

〔Example〕

FIG. 1 is a system configuration diagram showing an embodiment of the clock generator of the present invention. In the figure, the same symbols as in Figure 3 indicate the same or corresponding parts, and 2 is the DR.
This is a clock generator that includes a built-in circuit 21 that generates ready signals for multiple words that can also support AM nibble mode. That is, in this embodiment, in a system using a microprocessor 3, the clock generator 2 that generates the ready signal is notified that valid data is output to an external device when reading data from the microprocessor 3, and that valid data is output to an external device when writing data. It incorporates a ready signal generation circuit 21 that outputs ready signals for a plurality of transfer data indicating that the device has taken in data.

Therefore, in the system configured as described above, when the address of a device to be accessed by the microprocessor 3 is input to the address decoder/controller 1 as in the conventional case, a wait control indicating the wait number of the device to be accessed is performed. Signal WAITAQ-0 is output to clock generator 2. Then, this clock generator 2 generates a ready signal after inserting a necessary wait cycle based on the wait control signal WAITAo-m. Therefore, according to the word number control signal (woRD) output from the controller 1 at this time, a ready signal (READY) corresponding to the number of words to be transferred can be output to the microprocessor 3.

Therefore, according to this embodiment, seven ready signals synchronized by the ready signal generation circuit 21 in the clock generator 2 and the cyclic clock generation source can be outputted, so that the ready signal generation circuit 21 in the clock generator 2 can output seven ready signals synchronized with the cyclic clock generation source. This method has the advantage that the reliability of system operation is increased compared to a method in which a ready signal corresponding to a word is generated by an external circuit.゛In the above embodiment, the number of waits when generating one ready signal for multiple words is determined by the wait control signal WAITA.
I used the same thing for each wasid from o to m,
As shown in Fig. 2, the weight control signal WA for the first word is
It is possible to set the number of weights (time intervals) for each word by using the weight control signals WMUITBg-n corresponding to ITA'om and 2 to 4 words, and the same effect can be expected even with 9 weights.

〔Effect of the invention〕

As explained above, the present invention has a built-in ready signal generation circuit that outputs ready signals for multiple words, which is compatible with the KDRAM nibble mode in the clock generator. Since signals can be output, the reliability of system operation increases. Further, an external ready signal generation circuit is not required, and system design is also facilitated.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram using one embodiment of the clock generator of the present invention, FIG. 2 is a system configuration diagram using another embodiment of the present invention, and FIG. 3 is a system configuration diagram using a conventional clock generator. It is a system configuration diagram. 1...Address decoder controller, 2...
Clock generator, 3... microprocessor, 21... ready signal generation circuit.

Claims (1)

[Claims] A clock generator that generates a ready signal in a system using a microprocessor, and which indicates that valid data has been output to an external device when reading data from the microprocessor, or that data has been taken in by an external device when writing data. 1. A clock generator comprising a built-in ready signal generation circuit that outputs ready signals for a plurality of transfer data shown in FIG.