JPH04274083A - Data writing method - Google Patents

Abstract

PURPOSE:To shorten the time required for a memory access by performing a data writing processing with one access on a bit in words which are different at every memory element. CONSTITUTION:By independently generating the following signals, data is written in the memory element of a desired numbered bit by one access: a row address signal to each memory element 1 from an address information supply means (address generating circuit 3a) by the instruction of a control signal supply means (timing generating circuit 2a); a row address selection signal from the above-mentioned control signal supply means to the memory element of the desired numbered bit; a column address signal to each memory element 1 from the above-mentioned address information apply means by the instruction of the control signal supply means; and a column address selection signal from the above-mentioned control signal supply means to the memory element of the above-mentioned desired numbered bit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing method for writing data into a memory element in a storage device of a computer system that is accessed in units of words.

0002

2. Description of the Related Art FIG. 4 shows the configuration of a storage device in a conventional computer system, and for convenience, one word is shown with 16 bits, and the storage capacity is 1 megaword in total. In FIG. 4, a memory element 1 is a dynamic memory such as M5M41000AP manufactured by Mitsubishi Electric Corporation. 2b is a timing generation circuit that supplies control signals to each part of the storage device; 3b is an address generation circuit that generates 10-bit address information to be applied to the memory element 1 from 20-bit address information; 30 is a data selector;
When the terminal is at low level (hereinafter referred to as L level), the input signal to the A terminal (ADR0-9) is output to the Y terminal, and when the S terminal is at high level (hereinafter referred to as H level), the input signal to the B terminal (ADR0-9) is output to the Y terminal. ADR10-19) are output to the Y terminal. 4 is a write data register that holds write data to the memory element 1;

FIG. 5 shows the control timing of the storage device shown in FIG. 4. A0-9 in FIG. 5 are address signals to the A0-9 terminals of the memory element 1, including SEL (selection control signal), RAS (row address selection signal), and CAS.
(column address selection signal) and WE (write enable signal) indicate output signals of the timing generation circuit 2b. The control timing operation shown in FIG. 5 in this storage device is well known to those skilled in the art, and will therefore be omitted here.

0004

[Problems to be Solved by the Invention] In the conventional storage device as described above, address signals (A0-9) and control signals (RAS, CAS, W
Since all bit strings (D0 to D in Figure 4) that constitute a specific word are supplied in common, one write operation
I was only able to write 15). Therefore, if the bits of the data you want to write are distributed in different words,
Even if those bits are assigned to different memory elements 1, the data for each distributed word is read once and the bits of the data to be written are changed, and then the control timing operation shown in FIG. It was necessary to write the bit of data to be written into element 1.

The present invention has been made to solve the above-mentioned problems, and in addition to the conventional function of writing bits constituting a specified word at once, An object of the present invention is to obtain a data writing method that can write data to a plurality of bits assigned to a plurality of bits in one access.

[0006]

[Means for Solving the Problems] A data writing system according to the present invention includes address information supply means (address generation circuit 3a) for supplying common address information to each memory element 1 that stores bits constituting a word; control signal supply means (timing generation circuit 2a) for supplying write control signals independently to each of the memory elements 1;
A row address signal is sent from the address information supply means to each memory element 1 according to instructions from the control signal supply means, a row address selection signal is sent from the control signal supply means to the memory element of the desired bit, and the control signal supply means By independently generating a column address signal from the address information supplying means to each memory element and a column address selection signal from the control signal supplying means to the memory element of the desired bit according to an instruction, Data is written to the memory element in one access.

[0007]

[Operation] Control signal supply means (timing generation circuit 2a)
A row address signal is sent from the address information supply means (address generation circuit 3a) to each memory element 1 in response to an instruction from the control signal supply means, a row address selection signal is sent from the control signal supply means to the memory element of the desired bit, and the control signal supply means By independently generating a column address signal from the address information supplying means to each memory element 1 and a column address selection signal from the control signal supplying means to the memory element of the desired bit, the desired bit is determined. 1 in the memory element of
Data is written in one access.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention, and for convenience, one word is shown with 16 bits, and the memory device has a total storage capacity of 1 megaword. However, the present invention is not limited to or imposes any limitations on word size, storage capacity, etc. In FIG. 1, 1 is a memory element, for example M5M4100 manufactured by Mitsubishi Electric Corporation.
It is a dynamic memory like 0AP. 2a is a timing generation circuit as a control signal supply means for supplying control signals to each part of the storage device; 3a is a timing generation circuit that generates 10-bit address information to be applied to the memory element 1 from 20-bit address information and a mode signal from the timing generation circuit 2a; Address generation circuit as generating address information supply means, 4
is a write data register that holds write data to the memory element 1. The details of the address generation circuit 3a are omitted as they are not essential to the present invention, but MODE OU
a function of processing the input signals of ADR0-19 according to the T signal to generate address signals of address lines A0-9;
Specifically, when MODE OUT=“row address”, address signals ADR10-19 are sent to address lines A0-9.
It has a function of outputting a value obtained by adding S to address signals ADR0-9 to address lines A0-9 when MODE OUT="row address +S". Note that the above S is "+S0, +S1,...+S15" in FIG. 2, which will be described later.
It is a general term for.

Next, the operation of the data writing method of this embodiment will be explained. FIG. 2 is a control timing diagram showing an example of the operation. First, at time t1, the timing generation circuit 2a outputs a "row address" to MODE OUT, instructing the address generation circuit 3a to output a row address signal. After a certain period of time, the timing generation circuit 2a generates the RAS signal at time t2 to cause the memory element 1 to take in the row address. Thereafter, at time t3, the timing generation circuit 2a outputs "row address +S" to MODE OUT, and instructs the address generation circuit 3a to output column address +S. Further, a WE signal is generated before and after time t3 to instruct the memory element 1 to perform writing. After a certain period of time, at time t4, the timing generation circuit 2a
The AS0 signal is generated to cause the 0th bit memory element 1 to take in the column address and write data. Further, after a certain period of time, at time t5, the CAS0 signal is withdrawn and the access to the 0th bit memory element 1 is ended.

After the first bit, the control from t3 to t5 is repeated while changing the value of S to write the necessary data bit into the memory element 1 of the desired bit, and finally the RA
The S signal is withdrawn and the series of accesses ends.

FIG. 3 is a control timing diagram showing an example of the operation of another embodiment. In this example, from time t1 to time t
The operations up to 3 are the same as those shown in FIG. 2, but the MODE OUT issued at time t3 is "column address + S" where S is 0. At time t4, all CAS signals, that is, CAS
Issues everything from 0 to CAS15. By controlling in this manner, the conventional memory access shown in FIG. 5 can be performed.

According to each of the embodiments described above, the timing generating circuit 2a which provides an independent control signal to each memory element 1 activates only a part of the memory elements 1 constituting a word, and transmits data only to a specific memory element. In addition, by repeatedly using the control signal of the timing generation circuit 2a while the address generation circuit 3a, which generates address information to be given to all memory elements 1, generates different address signals, multiple memory elements belonging to different words can be written. It becomes possible to write data to the bits.

[0013]

As described above, according to the present invention, since an independent control signal is supplied to the memory elements constituting a word, for example, when changing a certain word, the contents of the bits of that word are changed once. There is no need to write the desired data bits again after reading all of the bits and changing the contents of the bits, and the process of writing data to bits in different words for each memory element can be done in one access. It is possible to reduce the burden on software and reduce the time required for memory access.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a storage device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the data writing method of this embodiment.

FIG. 3 is a timing chart for explaining the operation of a data writing method according to another embodiment.

FIG. 4 is a configuration diagram of a conventional storage device.

FIG. 5 is a timing chart for explaining the operation of a conventional data writing method.

[Explanation of symbols]

1 Memory element

Claims (1)

[Claims] 1. A storage device that is accessed in units of words consisting of a plurality of bits, comprising address information supply means for supplying common address information to each memory element storing bits constituting a word; control signal supply means for independently supplying a write control signal to each memory element, and a row address signal from the address information supply means to each memory element according to instructions from the control signal supply means; A row address selection signal to the bit-th memory element, a column address signal from the address information supply means to each memory element according to instructions from the control signal supply means, and a column address signal from the control signal supply means to the desired bit-th memory element. A data writing method characterized in that data is written into the memory element of the desired bit in one access by independently generating a column address selection signal.