JP2000163990A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate testing when the physical layout sequence and the physical data are taken into consideration by converting the logical addresses to secure the equality between the layout sequence of logical addresses and that of physical addresses included in a memory cell array and applying the inverse control to the write or read data based on the value of logical or physical addresses. SOLUTION: In a normal operation, an external logical address input is directly fetched inside, and a prescribed word line is selected in a memory cell array 1 when a MODE setting signal 16 is set at 'L' level. When the signal 16 is set at 'H' level, the logical address data are converted by an address scrambler 6, so that the sequence of the logical address data is coincident with that of the internal physical address data. Thereby the selection of word lines is carried out in a physical sequence. Then the sequence of physical addresses and that of logical addresses in the array 1 can be made the same by setting the signal 16 at 'H' level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a configuration and means of a semiconductor memory device for facilitating a test.

[0002]

2. Description of the Related Art In general, a semiconductor memory device is arranged in accordance with the arrangement order of logical address data specified from the outside in order to simplify the layout configuration of the storage device itself, to save the area, and to improve the circuit configuration. The arrangement order of the internal physical addresses is different. For example, DRAM (Dynamic Ra
In an ndom access memory (LDOM), logical row address data specified from outside is stored in LSB (Least Significant Bi
t), the corresponding internal physical address, that is, the selection of the word line is
WL (0) → WL (2) → WL (1) → WL (3) → ...
In many cases, the configuration is not selected in the physical order. The numbers in parentheses indicate the physical arrangement order.

Further, the value of the externally written logical data and the value of the stored data (physical data) in the storage device corresponding to the externally written logical data have different configurations depending on the stored address. This is the same for read data. For example, when logical data "1" is externally written to a certain address, depending on the specified address, the logical data is physically inverted internally to "0" and written internally. In some cases, the data is inverted to "1" and read as the logical data output "1".

[0004] As described above, due to the difference between the logical address order and the physical address order, and the difference between the logical data value and the physical data value (hereinafter referred to as “storage device-specific scrambling characteristics”), the storage device is actually used. When testing,
Using a scramble processing function provided in the test system for testing the storage device, the address, input data, and expected value data specified for the storage device are subjected to scramble processing corresponding to the scramble characteristics of the storage device, and the test is performed. That is common. In particular, when there is a defective portion in the storage device, it is necessary to know the exact physical address when analyzing the location and the value of the defective data, and the test is performed in consideration of the scrambling characteristic inherent to the storage device. It becomes more important to do.

[0005]

However, in recent years, semiconductor memory devices have become more sophisticated and diversified with the spread of system LSIs. Under such circumstances, the above-described scrambling characteristic inherent to the memory devices has been developed. As such, it is becoming more complex and diversified. Therefore, even when a test is performed using a semiconductor memory device test system,
A problem that the test program becomes complicated, or the scramble processing function of the test system alone cannot cope with the scrambling characteristic inherent in the storage device, and it is not easy to perform a test in consideration of the physical arrangement order and physical data in the storage device. A point has occurred.

The present invention has been made in order to overcome the above problems.
An object of the present invention is to provide a semiconductor memory device that can easily execute a test in consideration of a physical arrangement order and physical data inside the semiconductor memory device.

[0007]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of word lines and a plurality of bit line pairs, and a memory cell at each intersection of the word line and the bit line pair. And a semiconductor memory device having an address selecting means for selecting a specific physical address in the memory cell array, wherein the arrangement order of the logical addresses specified from the outside is determined in the memory cell array. An address scramble control circuit for converting a logical address so as to be equal to the arrangement order of physical addresses, and inverting write data from outside or reading data from the memory cell array according to the value of the logical address or the physical address. A data scramble control circuit for inversion control.

With this configuration, it is possible to easily perform a test in consideration of the physical arrangement order and physical data inside the semiconductor memory device by using the row address scramble control circuit and the data scramble control circuit corresponding to the scramble characteristic inherent in the semiconductor memory device. Can be performed.

Further, a semiconductor memory device according to the present invention is
A data scramble control circuit for controlling inversion of input / output data in accordance with a logical address value; an exclusive OR circuit of an output of the data inversion control circuit and an input data signal; It is desirable that the circuit be constituted by an exclusive OR circuit of the output of the control circuit and the output data signal. This is because logical data and physical data can be surely matched.

[0010] Further, a semiconductor memory device according to the present invention comprises:
It is preferable to further include an address generating circuit for generating desired address data by itself, and to supply the address data from the address generating circuit. By providing the internal address generation circuit, it is possible to execute a test in consideration of the physical arrangement order and the physical data inside the storage device without requiring an external address. This is because the test program in the test system can be simplified.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, 1 is a 64K bit memory cell array, WL (0) to WL (255) are word lines, and BL (0) to BL (255) and / BL (0) to //.
BL (255) indicates a bit line pair, 2 indicates a row decoder (word line driver), 3 indicates a row address latch circuit,
4 is a row address scramble control circuit, 5 is a selector, 6 is an address scrambler, 7 is a sense amplifier row, 8 is a column decoder, 9 is a write amplifier, and 1 is a write amplifier.
0 is a read amplifier, 11 is a column address latch (column predecoder), 12 is a data scramble control circuit, 13 is a data inversion control circuit, 14 is an I / O buffer, and 15 is an external logical address input. To 16
Indicates a mode setting signal, and 17 indicates data input / output.

Here, in the memory cell array 1, FIG.
A memory cell is arranged at the intersection of a word line and a bit line as shown in the figure. The data of the memory cell on / BL is written by inverting the physical data with respect to the external logical data and writing data on the memory cell on BL. The cell data is configured to write the same physical data as the external logical data.

The relation between the external logical address and the internal physical address and the relation between the external logical data and the internal physical data in the semiconductor memory device according to the present embodiment are as shown in (Table 1) to (Table 3).

[0015]

[Table 1]

[0016]

[Table 2]

[0017]

[Table 3]

In the semiconductor memory device having the above configuration, in a normal operation, the MODE setting signal 16 is set to "L" level so that the logical address input A0-7 from the outside is kept as it is as it is. The selected word line in the memory cell array 1 is selected through a row decoder (word line driver) 2 and transferred to a bit line, and the data of the memory cell corresponding to the selected word line is transferred to the bit line. The signal is amplified by the sense amplifier array 7. The word line selected at this time is as shown in (Table 1). Therefore, the selected word line when the external logical address is specified by incrementing from # 00 is not selected in the physical order.

Further, a specific bit line pair is selected via a column address latch (column predecoder) 11 and a column decoder 8, and data access is performed. In this case, as shown in (Table 3), the logical column address matches the physical column address.

At the time of data access, since the output of the data inversion control circuit in the data scramble control circuit 12 is at "L" level, externally written data is transferred from the I / O buffer 14 to the write amplifier 9 in a write cycle. The data is transferred as it is, and in a read cycle, the output data from the read amplifier 10 is output as it is via the I / O buffer. Therefore, when writing logical data "0", "0" is written as internal physical data in the memory cell on BL, and "1" is written as internal physical data in the memory cell on / BL. It is. That is, the data to be written depends on the row address, and is written in a specific address area in reverse.

In the operation when the MODE setting signal 16 is set to the "H" level in contrast to the normal operation as described above, the logical address data from the outside is in the same order as the internal physical address data by the row address scrambler 6. As shown in (Table 2), for example, when the external logical address data is specified by incrementing from “# 00”, the internal physical address, that is, the selection of the word line is not performed. Are performed in the proper order.

Further, the data scramble control circuit 12
When data is written to the memory cell on / BL by the function of, the external logical data is inverted and transferred to the write amplifier 9, so that the physical data finally written to the memory cell is external logical data. When the logical data “0” is externally written as shown in (Table 2) as in the case of the write data, the physical data written in the memory cell becomes “0” at all addresses.

As described above, by setting the MODE setting signal 16 to the "H" level, the physical address order in the memory cell array can be made the same as the logical address order, and the physical data is also set to the external logical data. Since it can be the same, a test assuming the physical address and the physical data in the memory cell array can be easily performed.

FIG. 2 is a configuration diagram of the row address scramble control circuit 4 in the semiconductor memory device according to the present embodiment. In FIG. 2, it is realized that the logical address is converted by the selector and the wiring connection such that the logical address arrangement order is equal to the physical address arrangement order in the memory cell array.

That is, when the logical addresses AX1 and AX2 are arranged in the reverse order as the physical address, the logical address AX1 is set to X2 and the logical address AX2 is set by setting the MODE setting signal 16 to the “H” level. X1
, The order of arrangement of logical addresses can be changed. In the actual row address scramble control circuit 4, by combining these circuits, it is possible to adjust the physical arrangement order corresponding to the scramble characteristics unique to the semiconductor memory device.

FIG. 3 shows a data scramble control circuit 12 in the semiconductor memory device according to this embodiment.
FIG. In FIG. 3, physical data inversion control is realized by a simple configuration of exclusive OR and logical product.

That is, when the logical addresses AX0 and AX2 are different, the inverted signal of the physical data is output by setting the MODE setting signal 16 to the "H" level. Therefore, in the physical data read test, if the physical data “1” is written at the physical address that should be read as “0”, the test is executed with the test inverted and corrected to “0”. If the physical data “0” is written at the physical address that should be read as “1”, the test is performed in a state where it is inverted and corrected to “1” in the test. Can be. The same processing can be performed in a physical data write test.

FIG. 4 shows an example of the semiconductor memory device according to the embodiment of the present invention. In FIG. 4, FIG.
The difference from the first embodiment is that the internal address generation circuit 18 and the selector 1
9 and a mode setting signal 20 are added.

According to the mode setting signal 20, the logical address data supplied to the semiconductor memory device according to the present embodiment can be switched to be supplied from the internal address counter. Therefore, the memory device can be switched without supplying an external logical address. A test can be executed in consideration of the internal physical arrangement order and physical data. Therefore, a test corresponding to the scrambling characteristic inherent in the semiconductor memory device can be reliably performed, and the test execution can be further facilitated and made more efficient.

As described above, according to the present embodiment, the physical arrangement order and the physical arrangement order inside the semiconductor memory device are achieved by using the row address scramble control circuit and the data scramble control circuit corresponding to the scramble characteristic inherent to the semiconductor memory device. A test considering data can be easily executed.

By providing the internal address generation circuit, it is possible to execute a test in consideration of the physical arrangement order and physical data inside the storage device without requiring an external address, thereby further facilitating measurement and storing data. It is possible to simplify the test program in the test system of the device.

[0032]

As described above, according to the semiconductor memory device of the present invention, the physical address inside the semiconductor memory device is increased by using the row address scramble control circuit and the data scramble control circuit corresponding to the scramble characteristic inherent in the semiconductor memory device. It is possible to easily execute a test in consideration of the physical arrangement order and physical data.

Further, according to the semiconductor memory device of the present invention, by providing the internal address generating circuit, a test can be executed in consideration of the physical arrangement order and physical data inside the memory device without requiring an external address. It is possible,
Further simplification of measurement and simplification of a test program in a storage device test system are possible. Particularly, in a semiconductor device in which various types of storage devices are built in a system LSI, the effect of reducing the number of test steps is enormous. .

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a configuration diagram of a row address scramble control circuit of the semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a configuration diagram of a data inversion control circuit of the semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a configuration block diagram of a semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 row decoder (word line driver) 3 row address latch circuit 4 row address scramble control circuit 5, 19 selector 6 address scrambler 7 sense amplifier column 8 column decoder 9 write amplifier 10 read amplifier 11 column address latch (column pre-register) Decoder) 12 data scramble control circuit 13 data inversion control circuit 14 I / O buffer 15 external logical address input 16, 20 mode setting signal 17 data I / O 18 address generation circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichiro Nomura 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5L106 DD11 DD23 FF04 FF05 GG05

Claims (3)

[Claims] 1. A memory cell array comprising a plurality of word lines and a plurality of bit line pairs, memory cells arranged at respective intersections of the word lines and the bit line pairs, and a specific memory cell in the memory cell array. A semiconductor memory device having address selection means for selecting a physical address, wherein the logical address is converted so that an arrangement order of an externally designated logical address is equal to an arrangement order of physical addresses in the memory cell array. Address scrambling control circuit, and according to the value of the logical address or the physical address,
And a data scramble control circuit for inverting write data from outside or inverting read data from the memory cell array. 2. A data inversion control circuit for performing an inversion control of input / output data according to a value of the logical address, and an exclusive control of an output of the data inversion control circuit and an input data signal. Logical OR circuit,
2. The semiconductor memory device according to claim 1, comprising an exclusive OR circuit of an output of said data inversion control circuit and an output data signal. 3. The semiconductor memory device according to claim 1, further comprising an address generating circuit for generating desired address data by itself, and supplying said address data from said address generating circuit.