JPH0724160B2 - Associative memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A plurality of words for storing a plurality of data and an address encoder section for receiving an address generation signal corresponding to the word and generating and outputting an address of the word are provided. In an associative memory device for determining a word to be rewritten from stored data based on a relationship between the data stored in each word and search data, at the same time as writing new data to the word, generating an address of the word A means for outputting a signal to the address encoder section is provided to improve throughput.

[Industrial application field]

According to the present invention, in an associative memory device that determines a word to be written from the relationship between stored data and search data, when writing data, the word address of the word to be operated is determined. The present invention relates to an associative memory device that can output simultaneously.

[Conventional technology]

An associative memory device is known in which a word to be written and read is determined from the relation between stored data and supplied search data, and writing and reading are performed. In this type of associative memory device, as disclosed in Japanese Patent Application No. 58-94525, data associated with the data (index) stored in the associative memory device is stored in a normal RAM (Ran).
In general, the dom access memory) device is used to access the RAM device using the word address of the word in which the index output from the associative storage device is stored. This is because the associative memory device is more expensive than the RAM device, and it is economical to store only the data (index) to be associated with the expensive associative memory device and store the other data in the inexpensive RAM device. The reason is that it is advantageous. Therefore, it is necessary to output the word address of the corresponding word from the associative memory device to the RAM device. FIG. 3 is an example of an associative memory device configured by using a CAM (content retrieval memory) and a RAM, which schematically represents the above-mentioned conventional example. Reference numeral 40 denotes a CAM which includes an ID (index) section 41 and an address encoder section 42. 43 is a RAM, which comprises an address decoder 44 and a data section 45. In search mode, enter the ID on the CAM40
Search the ID section 41 in AM40 and find the corresponding ID (for example, word #
When 1) is obtained, the search result match signal # 1 is output,
Input it to the address generation / output terminal of the address encoder # 1 of the address encoder unit 42, and output it.
Address of RAM43. In the RAM 43, the input address is decoded by the address decoder 44 to select the data part 45, and the selected data part is read out,
Access such as rewriting. However, in the conventional associative memory device of this type, when the data to be written is determined by determining the word to be written from the relationship between the stored data and the supplied search data, the word to which the data was written No means for outputting the address generation signal of No. 1 to the address encoder at the same time as the data write operation was provided, and therefore the word address of the corresponding word could not be output at the same time as the data write operation. . In order to output the word address, the write operation had to be repeated a plurality of times.

Further, as disclosed in Japanese Patent Application No. 55-151195 (Japanese Patent Application Laid-Open No. 57-74889), when writing data, a word in which data is written from among words in which valid data is not stored There is known an associative memory device having a means for determining a word and writing data in the determined word. The general usage pattern of this type of associative memory device is similar to that of the associative memory device described above. FIG. 4 shows a configuration example thereof, and the circuit shown is for one word,
In practice, the circuit is provided for each word. In the figure, reference numeral 1 is a signal line representing a search result from an associative memory cell section (not shown). When a corresponding word is selected by the search operation, a logical "1" signal is sent to this signal line 1. Given. 2 is a memory circuit, the first set terminal 3,
It has a second set terminal 4 and a reset terminal 5. The output line 6 of the memory circuit 2 is given to the selector 7. The selector 7 selects the signal of the signal line 1 indicating the search result during the search operation of the associative memory device, and selects the signal of the memory circuit output line 6 during the write operation. Reference numeral 8 denotes a multiple selection separation circuit, which selects and designates one word when one or a plurality of words are selected during a search operation and a write operation. 9 is a word line drive circuit, 10 is a word line of an associative memory cell, 11 is a first AND gate, 12 is a second AND gate, 13 is a first control line common to all words, and 14 is all words. A common second control line 15 is an all-word common set signal line for simultaneously setting the memory circuit 2 for all words. In the following description, it is assumed that the word line 10 takes a logic "1" during a read operation and a write operation.

The operation is as follows. During the search operation, the selector 7 selects the signal line 1 indicating the search result, and the word “1” is given to the signal line 1 for the word selected by the search. It is input to the selective separation circuit 8. When a plurality of words are selected, the multiple selection / separation circuit 8 instructs to select one word in relation to the multiple selection / separation circuits of other words, and the word line drive circuit 9 corresponding to that word is used to select a word line. The function as an associative memory device is achieved by driving 10 and reading a word.

Next, the operation when the stored information is initially written in the associative memory device will be described. First, a logic "1" is applied to the all-word common set signal 15 to set the memory circuits 2 for all the words.
At this time, in the selector 7, if the memory circuit output line 6 is set to be selected, the logic "1" of the memory circuit output line 6 is supplied to the multiple selection separation circuit 8 in all words,
The multiple selection separation circuit 8 selects one word from all the words. In this state, the first common to all words
A write operation is performed by applying a logic "1" to the control line 13 of. At this time, only the word line 10 of one word selected by the multiple selection separation circuit 8 takes the logic "1", and the stored information is written. In the word in which this writing is performed, the two inputs of the first AND gate 11 are both logic "1".
Therefore, the output of the first AND gate also takes the logic “1”,
The memory circuit 2 is reset. This means that, as will be apparent from the above description of the operation, the writing operation for this word will not be performed unless the memory circuit 12 is set in the future. In the word which is not written, the first control line 13 has the logic "1", but the word line 10 has the logic "0", and the output of the first AND gate 11 also takes the logic "0". The state of the memory circuit 2 does not change.

In the above description, the description has been made in the state where all the memory circuits of all words at the time of initial writing are set, but this is reset to those set in the memory circuit 2 of each word other than the initial writing. It is clear that the writing operation is performed in the same manner as the eyelid even in the state where the things are mixed. However, in this type of conventional associative memory device,
Based on the result of the search operation or the validity of the stored data, when determining the word to write the data and writing the data, the address generation signal of the word to which the data is written is Since there is no means for outputting to the address encoder at the same time as the data writing operation, the word address of the relevant word cannot be output at the same time as the data writing operation. In order to output the word address, the write operation had to be repeated a plurality of times.

[Problems to be Solved by the Invention] In the conventional associative memory device as described above, the word to which the data is to be written is determined based on the result of the search operation or the validity of the stored data. Then, when writing the data, there is no means provided with means for outputting the address generation signal of the word in which the data is written to the address encoder at the same time as the data writing operation,
Therefore, the word address of the corresponding word cannot be output at the same time as the data write operation. In order to output the word address, it is necessary to repeat the operation a plurality of times after writing the data. That is, after the write mode, it is necessary to output the word address of the word in which the data has been written in the read mode and access the RAM at the address.

As described above, in the conventional associative memory device, the word to be written is determined based on the result of the search operation or the validity of the stored data, and when writing the data, In order to output the word address of the written word, the write operation must be repeated a plurality of times, which has the drawback that the overall throughput cannot be improved.

[Means for Solving the Problems] In order to solve the above problems, the present invention receives a plurality of words for storing a plurality of data and an address generation signal corresponding to the words, An associative memory device having an address encoder unit for generating and outputting, when writing new data to the word, at the same time, it is provided with means for outputting an address generation signal of the word to the address encoder unit. And Further, the associative memory device stores a memory circuit that stores whether valid data is provided corresponding to each word, and a word that does not store valid data according to the memory state of the memory circuit. It is effective to have a means for determining a word to write data from the inside and writing data to the determined word. Further, it is effective that the means for outputting the address generation signal is formed by connecting the word line of each word to the terminal for instructing the address generation / output of the address encoder section.

[Operation] According to the present invention, the word to write the data is determined based on the result of the search operation or the validity of the stored data. It is possible to output to the address encoder section at the same time, so that the word address can be output at the same time when writing data. The output word address can be sent to, for example, the RAM section to access the data section for reading or writing. In order to output the word address as in the conventional case, after the write operation, It is not necessary to repeat the operation a plurality of times.

〔Example〕

FIG. 1 is a block diagram of an associative memory device which is a first embodiment of the present invention and is capable of outputting a word address simultaneously with writing of data. Although FIG. 1 shows the case of a two-word structure, it is needless to say that the present invention can be applied regardless of the number of words.

In FIG. 1, 101 and 102 are memory circuit groups for respectively storing data, 101 is a word line # 0, and 102 is a word line # 1. Reference numerals 103 and 104 are word lines driven when writing data to word # 0 and word # 1, respectively, and 103 is word line # 0 and 104 is word line # 1.
Is. 105 is a word line drive circuit # 0, and 107 is
This is the word line drive circuit # 1. Reference numeral 108 is a drive signal # 0 for instructing the word line drive circuit # 0 to drive the word line # 0, and 109 is drive for instructing the word line drive circuit # 1 to drive the word line # 1. This is signal # 1. In the associative memory device of FIG. 3 described in the section of the prior art, the drive signal is based on the relationship between the memory data and the applied search data.
108 and 109 are generated. The ID section 41 and the address encoder section 42 in FIG. 3 correspond to 141 and 142 in FIG.

In FIG. 1, 110 and 111 are address encoders for generating a word address, and 112 is an address output generated by the address encoder.
Reference numerals 113 and 114 are terminals for instructing address generation / output from the address encoder # 0 and the address encoder # 1, respectively, and are connected to the word line 103 and the word line 104, respectively. Address encoders 110 and 111 generate and output addresses according to signals input to terminals 113 and 114 that instruct address generation and output. A ROM (Read Only Memory) format is generally used as a means for implementing the address encoder, but when the ROM format is adopted, the terminals 113 and 114 are used.
Are each connected to each word line of the ROM.

FIG. 2 shows an embodiment in which the present invention is applied to the associative memory device of FIG. 4 capable of writing data into a word in which valid data is not stored, which is described in the section of the prior art. is there. Although the circuit itself of FIG. 4 is as described above and its explanation is omitted here, means (2,6,7,8 for deciding a word to write data from among words in which valid data is not stored is determined. ), A drive signal is generated to drive the word line 10 of the determined word. The word line 10 is an address encoder (here, 10) as in the case of FIG.
Terminal 115 for instructing address generation and output
Connected to.

The operation of the associative memory device of these embodiments will be described below.

Writing data without using a word address is performed by an associative operation or an operation of determining a word to write data from among words in which valid data is not stored,
Generate the drive signal corresponding to the word to write the data,
This can be realized by driving the word line of the word to which data is written based on the drive signal using a word line drive circuit. Here, the word line drive circuit is an amplifier circuit for driving a large load, and theoretically, in this case, the drive signal and the word line may be directly connected. When writing data, the word line of the word in which the data is written is always driven. Therefore, as shown in FIG. 1 or 2, the word line of each word is used for address generation / output of the address encoder. By connecting to the terminal to instruct, the drive signal is sent to the word in which the data is written, and at the same time, the drive signal is sent as the address generation signal to the terminal to instruct address generation / output of the address encoder, It can be seen that the word address of the word in which the data is written is generated and output by the address encoder. Since the word address is generated and output when the word line is driven, the word address of the word in which the data is written is output at the same time when the data is written. Although detailed description is omitted here,
Each block shown in FIGS. 2 and 3 can be realized very easily by using the present integrated circuit technology.

Although the embodiments have been described above, the present invention is not limited to these, and it is obvious that various modifications can be made within the scope of the claims.

〔The invention's effect〕

As described above, the present invention has the following advantages.

(1) Since the word address of the word in which the data has been written is output at the same time as writing the data, a high throughput can be realized when using this type of associative memory device.

(2) The range of applications of this type of associative memory is expanding with the sophistication of information processing, and the significance of realizing high throughput is extremely significant.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of another embodiment, and FIGS. 3 and 4 are diagrams showing a configuration of a conventional associative memory device. 101 ...... Word # 0 102 ...... Word # 1 103,104 ...... Word line 105,107 ...... Word line drive circuit 108,109 ...... Drive signal 110,111 ...... Address encoder # 0, # 1 141 ...... ID section 142 ...... Address ・Encoder part

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shinichiro Yamada 3-1, Morinosato Wakamiya, Atsugi City, Kanagawa Pref. Atsugi Telecommunications Research Laboratories, Nippon Telegraph and Telephone Public Corporation (56) Reference JP-A-59-220838 (JP, A) 57-74889 (JP, A)

Claims (3)

[Claims] 1. A plurality of words for storing a plurality of data,
In an associative memory device including an address encoder unit that receives an address generation signal corresponding to the word and generates and outputs the address of the word, at the same time when writing new data to the word, the address generation signal of the word An associative storage device comprising means for outputting to the address encoder section. 2. The associative memory device stores a memory circuit for storing valid data provided for each word, and valid data according to a memory state of the memory circuit. The associative storage device according to claim 1, further comprising means for determining a word to write data from among the unwritten words and writing the data to the determined word. 3. The means for outputting the address generation signal comprises:
The associative memory device according to claim 1 or 2, wherein a word line of each word is connected to a terminal for instructing address generation / output of the address encoder section.