JPH0520176A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the accesses of 8 and 16 bits by controlling both odd and even address selectors with use of an 8-bit/16-bit access switch signal and the least significant bit of an address bus. CONSTITUTION:A less significant 8-bit data bus 12 and a more significant 8-bit data bus 13 are provided, and a 1-adder 6 is provided between an address bus 11 and a decoder 5. The enable signal of the 1-adder 6 is equal to an AND of an 8-bit 16-bit access switch signal 10 and the least significant bit of the bus 11. That is, an odd address selector 3 and an even address selector 7 which are provided between the 8-bit storage element groups 1 and 4 and between the buses 12 and 13 respectively are controlled by the signal 10. Then an address signal is transmitted through the 1-adder 6 which is controlled by the OR of the signal 10 and the least significant bit of the bus 11. The output of the 1-adder 6 is applied to the decoders 2 and 5 and the selector 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art A semiconductor memory device is indispensable for constructing a system using a microcomputer, and signal transmission through the semiconductor memory device has become faster and has a larger capacity as the system becomes larger. Is required.

FIG. 2 shows an example of a conventional semiconductor memory device.
Will be explained. In FIG. 2, a group of 21 8-bit storage elements (hereinafter referred to as a memory cell) receives as an input a signal obtained by decoding an address signal of the lower 2nd bit and subsequent bits of a 29th address bus by a decoder 22 and the lower 2nd bit. The memory cell at the address indicated by the subsequent address signal becomes accessible. The selector 23 receives the address signal of the lower 2 bits of the address bus 29, the read signal 27, and the write signal 28, and selects the lower 2 bits of the address bus from the memory cells selected by the output of the decoder 22. If the address indicated by the bit is an odd address, the corresponding memory cell is selected, and if the read signal of 27 is in the read enable state, the data is sent from the selected memory cell to the data bus of read 30. If the 28 write signal is in the write enable state, the data on the 30 data bus is written to the selected memory cell.

A group of 24 8-bit storage elements (hereinafter referred to as a memory cell) receives as an input a signal obtained by decoding an address signal of the second lower bit of the address bus of 29 by a decoder of 25, and the second lower bit. The memory cell at the address indicated by the address signal becomes accessible. The selector 26 receives the address signal of the lower 2 bits of the address bus 29, the read signal of 27, and the write signal 28, and selects the lower 2 bits of the address bus from the memory cells selected by the output of the decoder 25. If the address indicated by is an even address, the corresponding memory cell is selected, and if the read signal of 27 is in the read enable state, the data is sent from the selected memory cell to the data bus of read 30. If the 28 write signal is in the write-enabled state, the data on the 30 data bus is written to the selected memory cell.

[0005]

However, in the above-mentioned conventional configuration, since only one address memory cell can be accessed at a time, only 8-bit data can be read and written.

The present invention solves the above-mentioned conventional problems, and provides a semiconductor memory device capable of two read / write operations of reading and writing 8-bit data and reading and writing 16-bit data. The purpose is to do.

[0007]

In order to achieve this object, a semiconductor memory device of the present invention comprises a first decoder having an address signal input terminal for the second and lower bits of an address bus and the first decoder. An 8-bit storage element group having an output as an input is provided, input / output terminals for an upper 8-bit data bus and a lower 8-bit data bus are provided, an address signal input terminal for the lower 2 bits of the address bus, and an 8-bit access / 16 Equipped with an odd address selector having a bit access switching signal input terminal, a read signal and a write signal input terminal, an address signal input terminal for the second lower bit of the address bus, an 8-bit access / 16-bit access switching signal And an adder that uses the logical product of the least significant bit of the address bus as an enable signal and the output of the adder An 8-bit storage elements for receiving the second decoder the output of the second decoder, the upper 8
Equipped with an input / output terminal for the bit data bus and the lower 8-bit data bus, the lower 2-bit address signal input terminal of the address bus, the 8-bit access / 16-bit access switching signal, and the logical product of the lowest bit of the address bus It is composed of an even address selector having an input terminal for a read signal and a write signal as an input.

[0008]

In the semiconductor memory device of the present invention, the odd address selector and the even address selector provided between the 8-bit memory element group and the data bus are controlled by the 8-bit access / 16-bit access switching signal, and the address signal is 8-bit. Pass through an adder controlled by the logical sum of the access / 16-bit access switching signal and the least significant bit of the address bus,
With the configuration in which the output is given to the decoder and the even address selector, when the 8-bit access / 16-bit access switching signal is the 16-bit access designation state and the least significant bit of the address bus is "1", the adder of the address bus Data added to the data is output, and the data can be transmitted between the corresponding 8-bit storage element and the upper 8-bit data bus by the even address selector. Then, the 8-bit storage element corresponding to the address of the address bus and the lower 8-bit data bus can transmit data via the odd address selector, and 16-bit data access becomes possible.

When the 8-bit access / 16-bit switching signal is in the 16-bit access designation state and the least significant bit of the address bus is "0", the 8-bit storage element corresponding to the address of the address bus and the lower 8-bit data are stored. Data can be transmitted between the buses via even address selectors, and the 8-bit storage element corresponding to the address in which the least significant bit of the address bus is replaced with "1" and the upper 8
Data can be transmitted between the bit data buses via odd address selectors, and 16-bit data access can be performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 1 is an 8-bit storage element group, 2 is a decoder, 3 is an odd address selector,
4 is an 8-bit storage element group, 5 is a decoder, 6 is a single adder, 7 is an even address selector, 8 is a read signal input terminal, 9 is a write signal input terminal, 10 is "0" and an 8-bit access state, " 1 "indicates an 8-bit access / 16-bit access switching signal input terminal indicating a 16-bit access state, 11 is an n-bit address bus, 12 is a lower 8-bit data bus, 13 is an upper 8-bit data bus, and 14 is an AND circuit. is there.

The operation of the semiconductor memory device of this embodiment having the above structure will be described below.

When the 8-bit access / 16-bit access switching signal (hereinafter referred to as the 8/16 switching signal) of FIGS. 1 and 10 designates 8-bit access and 11 address buses are even addresses, 2 The 8-bit storage element group (hereinafter referred to as a memory cell) of 1 indicated by the address signal of the lower second bit and thereafter of the address bus becomes accessible through the decoder of the address bus, but the address input to the odd address selector of 3 Since the lower 2-bit address signal of the bus is an even number, none of the odd-numbered address selectors are selected, and the memory cell of 1 can perform data transmission to both the 12 lower 8-bit data buses and the 13 upper 8-bit data buses. Absent. Then, the output of the AND circuit of 14 becomes "0" because the 8/16 switching signal is "0", and the adder of 6 does not perform the countable operation and the address of the address bus of 11 remains unchanged from 5 Decoder and 7 even address selectors. And the lower 2 of the address bus
The 4 memory cells indicated by the addresses on and after the bit are in the accessible state. Then, the memory cell indicated by the lower 2 bits of the address bus input to the even address selector of 7 is selected and the data can be transmitted to the data bus. At that time, the target data bus is the even address selector of 7. Since the 8/16 switching signal input to is 0, indicating an 8-bit access state, the lower 8-bit data bus is used.

When the 11-address bus is an odd address in the 8-bit access state, the 1-adder 6 does not perform the 1-add operation as in the case described above, and the 11-address bus is used as it is as the 5 decoders and the 7 decoders. To the even address selector of. However, since the lower 2 bits of the address input to the even address selector 7 are odd addresses, none of the even address selectors is selected.

Then, the memory cell of 1 indicated by the second and lower bits of the address bus from the decoder of 2 becomes accessible, and the lower 2 bits of the address bus input to the odd address selector of 3 are changed. The memory cell shown is selected, the 8/16 switching signal input to the odd address selector 3 is "0", and the 8-bit access state is set. Therefore, data transmission to the lower 8-bit data bus becomes possible.

When the 8/16 switching signal is "1", 16
In the case where the bit access is designated and the address bus of 11 is an even address, the output of the AND circuit of 14 is "0", and the 1 adder of 6 does not perform the 1 addition operation.
The address of the address bus of 11 is directly input to the even decoder of 7 and the even address selector of 7 and the memory cell of 4 indicated by the address signal of the second lower bit of the address bus is accessible via the decoder of 5. Become. Then, the memory cell indicated by the lower 2 bits of the address bus input to the even address selector of 7 is selected and the data can be transmitted to the data bus. At that time, the target data bus is the even address selector of 7. Since the output of the 14 logical product circuit input to is 0, it becomes the lower 8-bit data bus. Then, through the decoder of 2, the memory cell of 1 indicated by the address signal of the lower 2 bits of the address bus and thereafter becomes accessible, and the memory indicated by the lower 2 bits of the address bus inputted to the odd address selector of 3. A cell is selected and data transmission with the data bus becomes possible. At that time, the target data bus is the lowest of the address bus when the 8/16 switching signal input to the odd address selector 3 is "1". Since the bit is "1", it serves as an upper 8-bit data bus.

When the 8/16 switching signal is "1", 1
In the state where 6-bit access is designated, if the 11 address bus is an odd address, the output of the AND circuit of 14 becomes "1", and the 1 adder of 6 adds a signal to the address signal of the 11 address bus. To the decoder of 5 and the even address selector of 7. And by the decoder of 5,
The memory of No. 4 becomes accessible. Then, the memory cell indicated by the address signal of the lower 2 bits input to 7 is selected, and data can be transmitted to the data bus. Since the target data bus at that time is “1” at the output of the 14 logical product circuits input to 7, the upper 8
It becomes a bit data bus. Then, through the decoder of 2, the 1 memory cell indicated by the address signal of the second and lower bits of the address bus becomes accessible. Then, the memory cell indicated by the lower 2 bits of the address bus input to the odd address selector of 3 is selected and data can be transmitted to the data bus. At that time, the target data bus is the odd address of 3 Since the 8/16 switching signal input to the selector is "1" and the least significant bit of the address bus is "1", it is a lower 8-bit data bus.

As described above, according to this embodiment, one adder is provided between the address bus and the decoder to access the odd address selector and the even address selector by 8 bits.
By controlling with the 16-bit access switching signal and the least significant bit of the address bus, both 8-bit data access and 16-bit data access can be performed.

[0019]

According to the present invention, an adder is provided between the address bus and the decoder, and the odd address selector and the even address selector are controlled by the 8-bit access / 16-bit access switching signal and the least significant bit of the address bus. This enables both 8-bit access and 16-bit access of data, and 8-bit access / 1
It is possible to realize an excellent semiconductor memory device in which the access method can be arbitrarily changed by the 6-bit access switching signal and the use efficiency of the memory element group can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1,4 8-bit storage element group 2,5 Decoder 3 Odd address selector 6 One adder 7 Even address selector 8 Read signal 9 Write signal 10 8 bit access / 16 bit access switching signal 11 Address bus 12 Lower 8 bit data bus 13 Upper 8-bit data bus

Front page continuation (72) Inventor Shinichi Maruyama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.

Claims (1)

Claim: What is claimed is: 1. A first decoder having an address signal input terminal for the second and lower bits of an address bus and an 8-bit storage element group for receiving an output of the first decoder. , Input / output terminals for upper 8-bit data bus and lower 8-bit data bus, lower 2-bit address signal input terminal of address bus, 8-bit access / 16-bit access switching signal input terminal, read signal and write An odd address selector having a signal input terminal is provided, an address signal input terminal is provided, an 8-bit access / 16-bit access switching signal, a one-adder that uses the logical product of the least significant bit of the address bus as an enable signal, and one-add A second decoder that receives the output of the container and an 8-bit storage element group that receives the output of the second decoder, An 8-bit data bus and a lower 8-bit data bus are provided as input / output terminals, and the lower 2-bit address signal input terminal of the address bus, the 8-bit access / 16-bit access switching signal, and the least significant bit of the address bus A semiconductor memory device comprising: an even address selector having a logical product as an input and having input terminals for a read signal and a write signal.