JP2563537Y2 - Memory chip select circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement of a memory chip select circuit for selecting a memory chip having a designated address.

<Prior Art> Conventionally, as a chip select circuit of a memory, for example, there is a circuit shown in FIG.

The chip select circuit, the decoder 1 and ₂₁ to ₂₄
Are connected in two stages.

In this circuit it is supplied to the decoder 1 in the upper 2 bits A7~A6 of 8-bit address A7 to A0, decoder 2 ₁ to 2 ₄ are the Chip Select decoding signal of the decoder 1. Now 2 bits below the bit A7~A6 to the decoder ₂₁ to ₂₄
A5~A4 is given, the memory chip 3 ₁ to 3 ₁₆ is a chip select in the decode signal of the decoder ₂₁ to _24. Further, the memory chip 3 ₁ to 3 ₁₆ is given the lower 4 bits A3~A0 address, the memory chip there is finally the memory space specified by the address A7~A0 is selected.

<Problem to be Solved by the Invention> In the memory select circuit shown in FIG. 3, since the memory chip is selected using the decoded signal of the address as it is, the start address of the memory space in each memory chip and each memory chip The capacity of the chip is fixed.
For this reason, only memory chips of a predetermined capacity can be used, and addresses assigned to each memory chip are determined.

If an attempt is made to form a memory space in such a memory select circuit using several types of memory chips having different memory capacities, each memory chip has a fixed start address of the memory space, even though the memory space has a fixed start address. Since the size of the memory space formed by the chip differs depending on the memory capacity, even if an address is assigned, there may be no memory space corresponding to the address. That is, there is a problem that a gap is formed in the memory space.

The present invention has been made to solve such a problem, and even when a memory space is formed by using several types of memory chips having different memory capacities, a chip select of a memory that does not cause a gap in the memory space. It is intended to realize a circuit.

<Means for Solving the Problems> Decoders are connected in a plurality of stages, the next-stage decoder is chip-selected by a decode signal output from each stage, and a predetermined bit in the address is sequentially given to each stage decoder. A memory selection data supply means for transmitting allocation data defining a correspondence between the decode signal and the selected memory chip in a chip select circuit of a memory for selecting a memory chip based on a decode signal output from the last stage; As many as the number of generated decode signals are provided, chip selection is performed by the decode signals, and allocation decoders for decoding allocation data sent from the memory allocation data supply means are provided in the same number as the allocation decoders. Have been
An OR gate for taking the OR of the N-th (N is an integer) decode signal of each of the allocation decoders and chip-selecting the memory chip with this OR output. .

<Operation> In the present invention, the chip in the next stage decoder is selected by the decode signal output from each stage, so that the area in the memory space is sequentially selected in small area units. The memory chip is selected according to the allocation data by the allocation decoder and the OR gate provided between them.

<Example> Hereinafter, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, reference numeral 4 denotes a decoder, which decodes upper four bits A23 to A20 in a 24-bit address A23 to A0.

Reference numeral 5 denotes a decoder which is chip-selected by a decode signal of the decoder 4, and the decoder 5
The four bits A19 to A16 immediately below the bits A23 to A20 are decoded.

₆₁ through 65 ₁₆ are decoders, are chip select Te by the decode signal of the decoder 5. Each decoder 6 _1-6
16 is provided from the memory allocation data supply means 7
The 32-bit allocation data is decoded two bits at a time.

Here, the allocation data is data indicating the correspondence between the decode signal and the memory chip to be selected. The memory allocation data supply means 7 includes, for example, a register in which allocation data is set and a circuit for reading out the allocation data. With this configuration, the correspondence between the decode signal and the memory chip to be selected can be freely set by changing the allocation data set in the register.

8 _{1-8 4} is an OR gate, N th decoder 6 ₁ ~6 ₁₆ (N is an integer) takes the OR of the decoded signal each other in.

9 _{1 to} 9 ₄ are memory chips, and OR gates 8 ₁ to 8 ₄
Is selected by the output of. This chip select signal is set in accordance with the allocation data provided from the memory allocation data supply means 7.

In the circuit thus configured, a memory area in a memory space formed by a memory chip is selected by a decode signal of the decoder 4, and a memory area in the selected memory area is further selected by a decode signal of the decoder 5. I do. Decoder ₆₁ through _16, the decode signal S0~S15 coming from the decoder 5, in accordance split with data provided from the memory allocation data supply means 7, the OR gate 8
Select signal _{1-8 4} outputs ▲ ▼ ~ ▲
▼ Determine which of the following. Thus, addresses are assigned to the memory space formed by the memory chips according to the assigned data.

For example, the decoder 6 _and 62, 6 _3, 6 _4, 6 _{5-6 16} the split with the data of two bits given respectively (M00
1, M000), (M011, M010), (M021, M020), (M031, M03
0), (M041, M040) to (M0151, M150), (M001, M000) = (0,0) (M011, M010) = (0,0) (M021, M020) = (1,0) ( M031, M030) = (1,1) (M041, M040) = (0,0) ………………………………… (M151, M150) = (0,1) , Memory select signal ▲ ▼ ~ ▲
▼ is output at the address shown in FIG. Here, in FIG. 1, the circuit and the memory allocation data supply means 7 indicated by the broken line are connected to one decode signal line of the decoder 4, but the circuit and the memory allocation data supply means indicated by the broken line in FIG. 7 is also connected to other decode signal lines. In FIG. 1, only one circuit and one memory allocation data supply means 7 shown by a broken line are shown in order to avoid complicating the figure. 24-bit address A23
When the decoder 4 decodes the upper four bits A23 to A20 of .about.A0, one of the circuits indicated by the broken line connected to the decode signal line is selected. Therefore, the upper four bits A23 to A20 in the 24-bit addresses A23 to A0 are not masked when the chip is selected.

The circuit shown by the broken line in FIG. 1 may not be provided for all the decode signal lines of the decoder 4.

<Effects> According to the present invention, the following effects can be obtained.

Since addresses are freely allocated to the memory space formed by the memory chips by the memory allocation data supply means, even if several types of memory chips having different memory capacities are used, there is no gap in the memory space. Address can be assigned. As a result, even when a memory with an incomplete cost is desired, a memory chip having a large memory capacity and a memory chip having a small memory capacity can be combined, as if the combined memory existed from the beginning.

The circuit according to the present invention easily enters a gate array. At this time, if the allocation data is stored in a register and can be changed by software, addresses can be freely allocated without changing the hardware configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a correspondence relationship between a memory select signal and an address, and FIG. 3 is a diagram showing a conventional configuration example of a memory chip select circuit. is there. 4,5,6 _{1 to} 6 ₁₆ ... Decoder, 7... Memory allocation data supply means, 8 ₁ to 8 ₄ ... OR gate, 9 _{1 to} 9 ₄ .

Claims (1)

(57) [Scope of request for utility model registration] A decoder is connected to a plurality of stages, a next-stage decoder is chip-selected by a decode signal output from each stage, and a predetermined bit in an address is sequentially applied to each stage decoder. A memory selection data supply means for transmitting allocation data defining a correspondence between the decode signal and the selected memory chip in a chip select circuit of a memory for selecting a memory chip based on the output decode signal; and a decode signal generated from the last stage. And the number of allocation decoders, which are chip-selected by the decode signal and decode the allocation data sent from the memory allocation data supply means, are provided by the same number as the number of the allocation decoders. Nth (N is an integer) deco of each allocation decoder Taking an OR of the De signal each other, chip select circuit of the memory, characterized in that the memory chip in the OR output equipped with an OR gate for chip select, a.