JPS6224824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a redundant recombination system for storage devices in which duplication combinations can be recombined in a redundant storage device defect relief system.

In order to improve the yield of memory devices, the memory cell array is duplicated, and the same data is stored in each memory cell designated by the same address.
A duplication system for memory devices is known in which a defect existing in a memory cell array is relieved by outputting correctly stored data.

This method takes advantage of the fact that defects on a memory cell array are randomly scattered and it is almost impossible for memory cells at the same address to be defective at the same time.

However, when the number of defects exceeds a certain level, memory cells at the same address may become defective at the same time. Therefore, if one of the row line addresses that specifies the duplicated multi-bit data is changed, then the two multi-bit data specified by the same address will have a defect in at least one of them. There is a way to make it exist and save it.

However, according to this method, it is necessary to provide a function to change the address for all row lines, and although the relief effect is large, the increase in the amount of hardware for the address change function cannot be ignored from the viewpoint of yield or area. There were flaws.

In order to eliminate these drawbacks, the present invention is characterized by changing the combination of duplicated memory cell arrays instead of changing the address for each data of multiple bits, and its purpose is to improve the address change function. The goal is to reduce the amount of hardware and improve the yield of storage devices.

FIG. 1 shows an embodiment of the present invention, in which 1 is a dual system of memory cell arrays, 11A and 1.
1B is addressed so that the row line address of the 1st series memory cell array has a Hamming distance d _R =2, and the column line address has a Hamming distance d _C =1, so 2 ^dR+dC-2 = 2 The memory cell arrays 12A and 12B are address decoders for the memory cell arrays 11A and 11B, respectively, 2 is a two-system memory cell array that is duplicated, and 21A and 21B are one-system divided memory cell arrays. 22A and 22B are the address decoders of the memory cell arrays 21A and 21B, respectively; Output circuit 4 outputs correctly stored data among the data stored in the first and second system memory cell arrays, and 4 is address information.

In the illustrated example, each memory cell array 11A, 1
1B, 21A, and 21B are arrays each having one column line and four row lines. The 3-bit address information 4 is sent to address decoders 12A, 12.
Addresses are translated at B, 22A, and 22B to select one of the four row lines of the corresponding storage cell array.

FIG. 2 shows an example in which the row lines of storage cell arrays 11A, 11B, 21A, and 21B shown in FIG. 1 are addressed such that they have a Hamming distance d _R =2 within each array. It is.

In FIG. 2, vertical columns 11A and 11B of the table,
21A and 21B correspond to the column lines in the 1st and 2nd series, respectively, and the horizontal rows of the table correspond to the row lines.
Each 3-bit code represents an address at the intersection of a column line and a row line. Since the four codes in each column are coded with a Hamming distance d _R =2, the number of bits that change between vertically adjacent codes is two. Furthermore, for each system, two codes on the same row are coded with a Hamming distance d _C =1, so the number of bits that change between them is 1.

For example, when the address (000) in FIG. Ru. Furthermore, when the address (001) is accessed, the data specified by the address (001) of the memory cell arrays 11B and 21B is read out. The same operation is performed for each address below.

By the way, as mentioned above, if the memory cells at the same row address in both memory cell arrays 11A and 21A are defective and the memory device cannot be saved by duplication, the memory cell array 11
A combination of A and 21B may be salvageable.
In this case, generally one of the multiple bit addresses of the memory cell arrays 21A and 21B is
By inverting the address information of bit (d _R -1), duplication can be achieved by combining memory cell arrays 11A and 21B.

As a theoretical explanation, we will use the case of d _R =2 and d _C =1 in 3-bit address information, and explain that this holds true no matter which bit is inverted. First of all, in the binary number represented by 3 bits shown in Figure 3, if the information of the first bit is inverted, the corresponding decimal number (0←→1),
It can be seen that the positions of (2←→3), (4←→5), and (6←→7) are switched. Similarly, if the information of the second bit is inverted, (0, 1←→2, 3), (4, 5←→
It can be seen that when the information of the third bit is inverted, the positions of (0, 1, 2, 3←→4, 5, 6, 7) are switched. Moreover, in either case, the number represented by binary information neither increases nor decreases.

As shown in Fig. 2, the Hamming distance d _R = 2
Addresses are assigned to 11A, 11B and 21A, 21B while maintaining the same, thereby configuring the 1st and 2nd systems in FIG. As shown in Figure 2, 21A, 21B
When the information of the first bit of is inverted, 21A,
The corresponding addresses of 21B are swapped, and the (000) bit of 11A and the (001) bit of 21B, which were assigned the address first, can be accessed at the same time.

Also, if the information of the second bit of 21A and 21B is reversed, 21A's (000) and 21B's (010)
In this way, the addresses of 21A and 21B are swapped in a "cross-crossing" manner, and bits (000) of 11A and (010) of 21B, to which the addresses were originally assigned, can be accessed at the same time.

Similarly, if the information in the third bit of 21A and 21B is reversed,
Bits (000) of 1A and (100) of 21B can be accessed simultaneously.

At this time, the address space of 21A and the address space of 21B are simply exchanged, and the Hamming distance within each address space is not disturbed. Therefore, by inverting the information of the bit of one of the duplicated systems, the physical position of the bit of the other duplicated system can be changed.

This operation can be performed in exactly the same way even if the number of bits increases.

These exchange controls can be easily realized, for example, by providing inverter circuits on the input sides of address decoders 22A and 22B in FIG.

If address information (000) is entered from outside, 1
In the system, address (000) is accessed and the memory cell
Array 21A is selected. However, in the 2nd system, the address information of the least significant bit is inverted, so
Since the (001) address is accessed, the memory cell array 21B is selected.

The above is an example when the Hamming distance is d _R = 2, d _C = 1, but when d _R = 3, d _C = 1,
Each of the 1st and 2nd systems is divided into four memory cell arrays. For example, following the configuration shown in Fig. 1, the 1st system is 11A, 11B, 11C, 11
If the D and 2 systems are represented by 21A, 21B, 21C, and 21D, addresses can be allocated as shown in FIG. 4, for example.

In FIG. 4, by similarly inverting any of the first, second, and third bits of system 2, the corresponding sets of memory cell arrays of system 1 and system 2 can be swapped. can.

In this method, the above-mentioned method can be applied to the column lines of the memory cell array by taking the Hamming distance d _C (d _C >1), and the same effect can be expected.

As explained above, in this method, each _of the memory cell arrays divided into 2 ^dR+dC-2 (d _R ≧1, _{d C} ≧1, except for d Addresses are assigned so that the Hamming distances of any two row and column addresses included are greater than or equal to d _R and d _C , respectively, and one of the duplicated address information is set to d _R -1 and d _C By inverting only the bit given by -1, the duplex memory cell array can be recombined in 2 ^dR+dC-2 ways.

FIG. 5 shows the address decoder 2 in FIG.
This figure shows a specific example of the configuration of 2B. Note that the address decoder 22A has a similar configuration.

In FIG. 5, 21B is a memory cell array;
22B is an address decoder, 4 is 3-bit address information, 5 is a duplex recombination inverter, 6 is a switch, 7 to 9 are address buffers, 10
1 to 13 represent row lines.

The specific operation of the address decoder 22B begins with address buffers 7, 8, and 9 receiving address information 4. address buffer 7,
As shown in the figure, 8 and 9 send out two signals: address information 4 and its inverted information. This signal
Whether each transistor in the address decoder matrix receives or not is determined by whether or not a wire is connected to the gate, and addressing is performed so that one row line is uniquely selected.

Therefore, in order to recombine the duplication of 11A, 21A and 11B, 21B to the duplication of 11A, 21B and 11B, 21A, switch 6 as shown in the figure and input the address through the duplication recombination inverter 5. This can be achieved by providing information.

The amount of hardware required for recombination is just to add one stage of inverter circuit to the address bits that you want to invert.In terms of operation, if you want to recombine duplication, you can use it via an inverter, or if you do not want to recombine, you can use it via an inverter. Supply addresses without going through an inverter.

Therefore, the relief effect of duplication can be enhanced with an extremely small amount of hardware.

As explained above, since a duplex memory cell array can be recombined with a small amount of hardware, it can be applied to storage devices where there are always some defects that cannot be repaired without recombination. As a result, an extremely high yield can be obtained with almost no area burden on the storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a row address configuration diagram of the memory cell array shown in FIG. 1, FIG. 3 is an explanatory diagram of the bit reversal effect, and FIG. 4 is d _R FIG. 5 is an explanatory diagram of an example of address allocation when d C =3 and d _C =1. FIG. 5 is a block diagram of the address decoder shown in FIG. 1. In the figure, 1 is a 1-system memory cell array, 11A,
11B is a 1-system divided memory cell array, 1
2A and 12B are address decoders, 2 is a 2-system storage cell array, 21A and 21B are 2-system divided storage cell arrays, 22A and 22B are address decoders, and 3 is an output circuit.

Claims (1)

[Scope of Claims] 1. Data is stored in the memory cells specified by the same address in each of the duplicated first system storage cell array and second system storage cell array, and the system data is stored correctly. In _a duplication system for ^a _storage device _that outputs
+d _C ≥ 3), and the Hamming distance of any two row addresses included in each of the divided storage cell arrays is d _R or more, and the Hamming distance of any two column addresses included in each of the divided storage cell arrays is Addressing is performed so that the Hamming distance is d _C or more, and the memory cell array of the first system or the memory cell array of the second system is
Any d _R −1 (d _R ≥
2) Arbitrary d _C -1 (d _C ≧2) A duplex set of memory devices characterized by inverting at least one of bit address information and selecting any 2 ^dR+dC-2 combinations of memory cell arrays to be duplexed. Replacement method.