JPS5935120B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device that automatically switches to a spare memory device.

Many memory devices have been proposed that enable use by switching to a spare memory device in order to remedy failures or manufacturing defects.

Japanese Patent Application No. 54-3598 discloses that in a redundant memory device having more than the originally required number of memory units consisting of a memory cell array, decoder, timing circuit, etc., each memory unit can be switched to a spare by an identification signal. Discloses a method to do this automatically. FIGS. 1 and 2 show an example of a configuration using this nine method.

The memory device 1 is composed of n memory units 2. Each memory unit 2 consists of a switching circuit 3 and a memory section 4. The switching circuit 3 receives the unit address 5 and the identification signal 6, and sends an activation signal 7 to the memory section 4 and an identification signal 6 to the switching circuit 3 of the adjacent memory unit 2. Here, the unit address 5 is a part of the accessed address that specifies the memory unit 2, and the identification signal 6 has a one-to-one correspondence with the unit address 5. The memory section 4 has a general (known) configuration, operates based on an intra-unit address (including a read/write control signal) 8 and an activation signal □, and transmits and receives a data signal 9 onto a data bus 10 . FIG. 2 shows an example of the configuration of a switching circuit, in which the switching circuit 3 includes a flag 11, a matcher 12,
It is composed of an arithmetic circuit 13, a selection circuit 14, and an AND circuit 15.

Flag 11 is “1” when memory unit 2 is “good”.
The matcher 12 outputs a signal 16 which is 0'' when the unit address 5 is defective.The matcher 12 outputs a signal 16 which is 0'' when the unit address 5 and the identification signal 6 match.
', and the logical AND of this output and the signal 16 from the flag 11 is outputted as the activation signal 7 by the AND circuit 15. When the memory device 1 of FIG. 1 originally requires k high-quality memory units, the arithmetic circuit 13 outputs an identification signal 6 corresponding to a unit address 5 specifying them. ．．
If expressed as Al, A2, ..., Ak-1, an operation that generates A1+1 for any Ai (for example, 1
This is a circuit that performs the calculation (addition of 1) and outputs the calculation result 17. The selection circuit 14 selects the operation result 17 when the signal 16 indicates "good", and selects the input identification signal 6 when the signal 16 indicates "defective", and sends the identification signal to the adjacent memory unit 2. Send as 6. It will be explained below that with the above configuration, it is possible to automatically switch between a ``defective'' memory unit and a spare memory unit. Now, suppose that the leftmost memory unit 2 in the memory device 1 in FIG. k-1, an adder circuit of 1 is used as the arithmetic circuit 13, and the identification signal 6 input to the leftmost memory unit 2 is 'O'. first,
The leftmost memory unit 2 is defective, so the flag is set to 1.
If it is 1, O' is output, and the activation signal 7 is inhibited by the AND circuit 15, so the memory unit is disconnected. In addition, the identification signal 6 to the next memory unit remains 0, and this second memory unit is activated with the matcher 11 outputting ``1'' only when the unit address 5 is ``O''. In other words, it equivalently replaces the leftmost memory unit.On the other hand, the identification signal to the third memory unit is +1 + 1'' transmitted by the adder circuit, and it is activated at the unit address 1''. become. Other memory units also perform the same operation as above depending on their "good" or "bad" status, and as a result, k "good" memory units from the leftmost end in FIG. 1 are used, so 8. The defective memory unit will be separated and the spare memory unit will be installed automatically.However, in the above switching method, the unit of switching is fixed to the physical size of the memory unit, so failures may occur. Another drawback is that there is a limit to the ability to repair defects.

For example, in general, reducing the size of the memory unit and increasing the degree of freedom in switching will improve the rescue ability, but if the entire memory device is configured as a large LSI and there is a limit on the total amount of hardware, Due to the X division loss due to the smaller unit and the increase in the wiring area, the proportion of spare parts in the whole decreases. Therefore, the improvement in manufacturing yield due to defect relief is not so great. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device in which the switching unit can be made smaller than the memory unit without causing division loss.

Therefore, the present invention divides a memory unit into a plurality of memory blocks, and accesses a normal memory block using a switching circuit provided for each memory block, so that a memory block smaller than the memory unit can be accessed. This allows for unit-based switching.

FIG. 3 shows the correspondence between the logical division of memory units and address information in the present invention.

A memory section 4 in each memory unit is a memory cell array 1.
8, an X decoder 19, a Y decoder 20, and a common circuit 21 consisting of a timing circuit, a sense up, etc. On the other hand, the address information 22 includes a unit address 5 specifying a memory unit, a row direction address (X address) 23 inputted to the X decoder 19, and a column direction address (Y address) 24 inputted to the Y decoder 20.
It consists of At this time, the memory cell array 18 uses 2X bits (called the X block address) 25 in the It is logically divided into blocks 27. In the present invention, switching is performed using this memory block 27 as a unit. FIG. 4 conceptually shows an embodiment of the present invention, in which the memory device 1 is composed of n memory units 2 as in FIG. Each memory unit 2 has a memory section 4
, 2X×2y switching circuits 3, and a conversion circuit 28 including memory unit activation means. Address information 22 for accessing this memory device 1 includes a block address 29 consisting of a unit address 5, an X block address 25, and a Y block address 26.
Addresses 30, . It is divided into 31 addresses within the Y block. The memory section 4 in each memory unit 2 has a third
As shown in the figure, the memory block is logically divided into 2X×2y memory blocks designated by block addresses 29. The switching circuit 3 has a one-to-one correspondence with this memory block, and its configuration is the same as that shown in FIG. The flag 11 indicates whether the memory block corresponding to the switching circuit is good or bad. Also, instead of unit address 5, block address 29,
As the identification signal 6, a signal corresponding to the block address 29 on a one-to-one basis is received. Further, the output activation signal 7 is inputted not directly to the memory section 4 but to the conversion circuit 28. When the activation signal 7 is output from any of the switching circuits 3 in the memory unit 2, the conversion circuit 28 activates the memory section 4 and converts the switching circuit 3 to which the activation signal was output to X.
An X block address 25 and a Y block address 26 specifying a memory block 27 corresponding to the block are generated and input into the memory section 4. The memory unit 4 stores the X block address 25 and Y block address 26 from the conversion circuit 28.
, and the address 30 in the X block and the address 31 in the Y block from the accessed address information, select and drive the memory cell, and transfer the data signal 9 to the data bus 1.
Send and receive on 0. With the above configuration, each switching circuit 3 performs the operation as explained in FIG.
Different identification signals are input to all switching circuits corresponding to good memory blocks in each memory section.

Therefore, there is only one switching circuit 3 in the entire memory device 1 that outputs the activation signal 7 in response to an accessed block address, and at this time, the conversion circuit 28 accesses the block corresponding to this switching circuit. The address is converted as follows. On the other hand, a "defective" memory block is prohibited from outputting the activation signal 7 of the corresponding switching circuit, so it will not be accessed. In this way, automatic switching is performed in units of logically divided memory blocks. Figure 5 shows x-1, y-
1 is a more specific example of the configuration of the memory unit 2.

The memory cell array 18 corresponds to 60-1 bits of each 1-bit X block address and Y block address (
It is divided into four memory blocks: 00), (01), (10), and (11). The conversion circuit 28 is an OR circuit 32
, 33, and 34. When the activation signal "7" is output from any one of the four switching circuits 3 corresponding to each memory block, the OR circuit 32 transfers it to the common circuit 21 and activates the memory. circuit 33
, 34 encode the starting signal 7 from each switching circuit, and the X block address 25 and the Y block address 26.
It is output to the X decoder 19 and Y decoder 20 as follows. In a memory unit configured in this way, for example, in the second switching circuit from the left end, the block address 2
9 and the identification signal match, and the flag indicates "good", so it is assumed that the activation signal 7 is output.At this time, the OR circuits 33 and 34 select the X block address 2.
5 becomes ``0'', Y block address 26ba1'', (
01) is accessed. The same applies to other switching circuits, and the memory block corresponding to the switching circuit outputting the activation signal will be accessed. FIG. 6 is an explanatory diagram of switching when the memory unit shown in FIG. 5 is used.

It is assumed that among the memory units shown in the upper row, the shaded portions are ``defective'' memory blocks. In this case, if units 0 and 3 have a fault in the X decoder (or word line) or Y decoder (or bit line) and this causes a fault in either the This assumes that there is a disability. The flags corresponding to these memory blocks are shown in the next stage as "good" - 1 and "bad" = 0.Thereby, the identification signal input to each switching circuit is the same as the identification signal input to unit 0. If it is set to ``O'', the result will be as shown in the lower row.Only when these identification signals and the accessed block address match and the flag indicates ``1'', the memory at the address shown in the lowermost row will be processed. The block will be accessed.As is clear from Figure 6,
Since the identification signals corresponding to the memory blocks whose flag indicates "good" are all different, and all the blocks that are actually accessed are good blocks, this configuration allows only the "good" memory blocks to be selected. - A driven memory device is realized.Although the present invention uses a part of both the row direction address and the column direction address as the block address, it is naturally possible to use only the row direction address or the column direction address. It can also be changed to

However, if only row-direction addresses (column-direction addresses) are used, there is a drawback that the entire memory unit must be treated as defective in the case of a failure that extends throughout the column direction (row direction). Not even. As explained above, according to the present invention, a memory cell array is logically divided, and a match between a block address and an identification signal is detected by a switching circuit corresponding to each divided memory block. By generating an address specifying a block corresponding to a switching circuit, switching can be performed in units of memory blocks, resulting in the following advantages.

(1) The switching unit is a logically divided memory block, which can be made smaller than a memory unit without causing division loss (though the number of switching circuits increases). Therefore, it is recommended that the entire memory device be configured with a large LSI. In that case,
It is possible to increase the manufacturing yield improvement rate due to defect relief.

(2) Since division is performed in both the row and column directions, if all memory cells in the X or Y direction become faulty, such as a fault in the X decoder (word line) or Y decoder (bit line). However, since there is no need to make the entire memory cell array unusable, memory usage efficiency is high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing a specific example of the switching circuit shown in FIG. 1, and FIG. 3 is a diagram showing the correspondence between logical division of a memory unit and address information in the present invention. , FIG. 4 is a block diagram showing one embodiment of the present invention, FIG. 5 is a diagram showing one memory unit when x-y=1, and FIG. 6 is a diagram showing one memory unit using the memory unit shown in FIG. 5. FIG. 3 is a diagram illustrating an example of switching between cases. DESCRIPTION OF SYMBOLS 1...Memory device, 2...Memory unit, 3...Switching circuit, 4...Memory section, 5...Unit address, 6...
...Identification signal, 7...Start signal, 8...
・Intra-unit address, 9...Data signal, 1
0...Data bus, 11...Flag,
12... Matcher 13... Arithmetic circuit, 14... Selection circuit, 15... AND circuit, 16... Failure signal, 17...
Operation result, 18...Memory cell array, 19.
...X decoder, 20...Y decoder,
21...Common circuit, 22...Address information, 23...X address, 24...
Y address, 25...X flock address, 2
6...Y block address, 27...
Memory block, 28... Conversion circuit, 29...
. . . Block address, 30 . . . Address in X block, 31 . . . Address in Y block, 32, 33, 34 . . . OR circuit.

Claims (1)

[Claims] 1 Consists of multiple memory units, each memory unit is divided into multiple memory blocks, and a switching circuit is provided for each memory block, and each switching circuit displays whether the corresponding memory block is "good" or "bad". The display means outputs an identification signal corresponding to a block address specifying a memory unit and a memory block.
When it indicates "good", it is an identification signal that has never been generated, and when it indicates "failure", it is propagated as it is to the next switching circuit, and the propagated identification signal is used as the above block address. Comparing means for making a comparison, and means for generating a signal for driving a corresponding memory block based on a match signal from the comparing means and a "good" indication from the display means, and in each memory unit, a signal is generated from the switching circuit. A memory device characterized in that access is performed based on a drive signal and an intra-block address.