JPS61992A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To vary the bit constitution of a memory by reading and writing selectively data from and on plural memory cell arrays having the same word and bit constitutions. CONSTITUTION:Since there are two memory cell arrays 1 having the constitution of (8k words)X(4 bits), this memory has the 64k-bit storage capacity as the whole. In case that this 64k-bit RAM is used as a memory having the constitution of (8k workds)X(8 bits), a selecting signal 23 and a -CS signal 8 are set to the low level to turn off a bus connection switch 16, and the 8-bit width (D0-D7) is secured with respect to a data bus. Switching between input buffers 11 and 14 and output buffers 12 and 15 is performed by a -WE signal 9. In case that data of the 4-bit width is handled, that is, the memory is used as an RAM having the constitution of (16k works)X(4 bits), the selecting signal 23 is set to the high level, and the -CS signal 8 is set to the low level, and a data bus 10 of lower bits is used as the 4-bit data bus.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a circuit configuration of an LSI memory.

Conventional Structures and Their Problems In recent years, LSI memory devices have become faster and larger in capacity, and the bit structure of the memory is becoming more diverse. 1,
Memories with a 4.8-bit configuration have been developed as RAMs and static RAMs, respectively, but their configurations are fixed and the bit configuration cannot be changed freely.

Conventional LSI memory (64 RAM) is shown below.
The circuit configuration will be explained with reference to FIG. In FIG. 1, 1 is a memory cell array, and 8 has a hood x 8 focus configuration. Reference numeral 2 denotes an address bus for addressing the hood 8, which is composed of 13 Natres lines 1, . . . A12. 3 is an 8-bit wide data bus (D0 to D7), and data input buffer 74 and output buffer 6 are controlled by control lines 6 and 7, respectively.

The signals on control lines 6 and 7 are chip select signal 8 (CS
) and the write enable signal 9 (W'E), W
The data write mode and read mode are switched by the E times signal. Therefore, data is always read/written in 8-bit units.

In this way, in the above example, the bit configuration of the RAM is fixed at 8 bits, so if you try to read or write data with a different bit configuration, for example 4 bits, the address space will be fixed at 8. Because there is, there is food x 4 on 8.
The problem is that only the storage capacity of 32 bits (half the bit of 64 bits) can be used, and the usage efficiency is extremely low. Each had to be used.

Purpose of the Invention The present invention aims to solve such conventional problems by changing the bit configuration of an LSI memory from a fixed one to a variable one, and selecting the bit configuration of the memory in accordance with the bit width of data to be handled. .

Structure of the Invention The present invention enables selective reading and writing of a plurality of memory cell arrays having the same food and bit configuration.
The bit configuration of memory is variable.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a circuit configuration of an LSI memory according to an embodiment of the present invention, and the numbers of the components common to the conventional example are the same as in FIG. 1. 1 is a memory cell array having an 8-hood x 4-bit configuration, and since there are two sets of these, it has a total storage capacity of 64 bits.

Address bus 2 (Ao-A12) is commonly used to address the two sets of memory cell arrays. 10
is a lower 4-bit width data bus (DO-D3),
It is connected to the in-cover sofa 11 and the out-cover sofa 12.

Similarly, 13 is a data bus (D4 to D7) with a width of the upper 4 bits.
) and is connected to the input buffer 14 and the output sofa 16. 16 is a switch for connecting the lower 4 bits and upper 4 bits of the data bus, and the control line 2
1.

The input buffers 11, 14 are controlled by control lines 17, 19, respectively, and the output bass valves 12, 15 are controlled by control lines 18, 20, respectively.

The control lines 17 to 21 above are the chip select signal 8 (
C3L! =Lie M Neve/L=Signal 9 (WE) combination
.

Address signal 22 (A13) for address extension
and a selection signal 23 (4/85 select) for switching the data bit width between '8 pits and 4 bits.

When using this 64-bit RAM in an 8-bit configuration, the selection signal 23 and the C8 signal 8 are set to low level Nislever, and the hash Jfl switch 16° is turned off, so the data bus has an 8-bit width (D0 ~D7) is ensured. Input buffer 11.14 and output Banoff 712,
15 is switched by the WE signal 9. For example, when WEs goes low level, the input buffer 11.1
4 is enabled, the data of the lower 4 bits and upper 4 bits of the data bus are written to the same location in the memory cell array specified by the common address bus.

(Write mode) Conversely, by setting the WE signal 9 to a high level, 8-bit wide data can be read from the RAM onto the data bus (read mode).

On the other hand, if you want to handle 4-bit data, that is, 16
When using it as a RAM with a hood x4 bit configuration, set the selection signal 23 to high level, set the m signal 8 to low level,
The lower 10 will be used as the 4-bit data bus. Address signal 22 for address expansion (hereinafter A13
It is written as ) to low level, the bus connection switch 16
Since the input buffer 7A14 and the output buffer 16 of the upper 4 bits F and (S) are in the OFF state, the 4-bit data is read and written to 8 via the input buffer 711 and the output buffer 12. Next, when A13 is set to high level, the input buffers 11 and 712 of the lower 4-bit bus remain in the OFF state, and the switch 16 becomes ON, so that the 4-bit data is transferred to the input buffer 71.
4. The data for the hood is read/written to the other memory cell array 8 via the output buffer 15.

According to the above embodiment, the storage capacity is 64 bits R
AM can be used not only in an 8-hood x 8-bit configuration, but also in a 16-hood x 4-bit configuration.

Effects of the Invention As described above, the present invention arranges cell arrays with the same memory configuration (number of hoods x number of bits), connects a data bus with the same bit width as the cell arrays to the cell arrays via input/output buffers, and By selectively activating the input/output buffer 7 and selectively connecting the data buses to each other,
Data of a desired bit width can be read or written to an address specified by an address bus. Therefore, by using the semiconductor memory according to the present invention, since the bit width of data can be changed, it is possible to connect to an 8-bit bus or a 4-bit bus, and moreover, the storage capacity of the memory can be used without wasting it.

In this way, the present invention makes it possible to realize a semiconductor memory in which the bit width of data can be selected, is highly versatile, and has high memory usage efficiency.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional LSI memory, and FIG. 2 is a circuit diagram of an LSI memory according to an embodiment of the present invention.

Claims (1)

[Claims] a plurality of memory cell arrays having the same number of hoods and the same bit width; a plurality of data buses having the same bit width as the memory cell arrays; and means for selectively activating input/output buffers of the data buses; 1. A semiconductor memory comprising means for selectively connecting data buses to each other.