WO2006027920A1 - Nonvolatile semiconductor storage device - Google Patents

Abstract

A nonvolatile semiconductor storage device comprises a plurality of memory cells having magnetic resistance elements, a write data processing circuit for feeding the individual memory cells with write data to be written therein, and a read data processing circuit for processing the read data to be read out from the memory cells, thereby to create output data to be outputted to the outside. At the writing action, the write data processing circuit feeds common write data to an n-number (n: an integer of 2 or more) of memory cells. At the reading action, the read data processing circuit determines one output data on the basis of the n-number of read data individually read out from the n-number of memory cells. In case the n indicates an odd number, the read data processing circuit determines one output data from the n-number of read data by performing a majority rule operation.

Description

 Specification

 Nonvolatile semiconductor memory device

 Technical field

 The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a magnetoresistive element.

 Background art

 [0002] In recent years, with the rapid spread of mobile phones and the like !, there is an increasing demand for memories having nonvolatile characteristics, large capacity, low voltage operation, and low power consumption characteristics. Magnetic Random Access Memory (MRAM) is expected as a memory with these characteristics.

 [0003] The MRAM includes a tunnel magneto resistance (TMR) element in a memory cell. 1A and 1B are conceptual diagrams showing the configuration of a general TMR element. The TMR element 1 has a free ferromagnetic layer (free layer) 2, a tunnel insulating layer 3, and a fixed ferromagnetic layer (pinned layer) 4. The tunnel insulating layer 2 is divided into a free layer 2 and a pinned layer 4. It is shaped to be pinched. The direction of the spontaneous magnetization in the pinned layer 4 is fixed at the time of manufacture. In contrast, the direction of the spontaneous magnetic field in the free layer 2 can be reversed by the current flowing above and below the TMR element 1.

[0004] This TMR element 1 can take two states depending on the direction of the spontaneous magnetic field in the free layer 2 (see the arrow in the figure). Specifically, as shown in FIG. 1A, in one state, the direction of the spontaneous magnetic field in the free layer 2 and the direction of the spontaneous magnetic field in the pinned layer 4 are “parallel” ( Parallel state). Further, as shown in FIG. 1B, in the other state, the direction of the spontaneous magnetic field in the free layer 2 and the direction of the spontaneous magnetic field in the pinned layer 4 are “antiparallel” (antiparallel state). At this time, it is known that the resistance value (R + AR) of the TMR element 1 in the “anti-parallel state” becomes larger than the resistance value (R) of the TMR element 1 in the “parallel state” due to the tunnel magnetoresistance effect. Yes. The MRAM stores data by utilizing the change in the resistance value of the TMR element 1. For example, “parallel state” corresponds to the data value “0”, and “antiparallel state” corresponds to the data value “1”. Also, the data stored in the memory cell can be read. The protrusion is performed by detecting the change in the resistance value.

FIG. 2 is a schematic diagram for explaining the principle of writing to a memory cell provided with such a TMR element 1. As shown in FIG. 2, the TMR element 1 is interposed between a word line WL (write word line) along the X direction and a bit line BL along the Y direction. The X direction indicates, for example, the “easy magnetic axis direction” of the spontaneous magnetism in the TMR element 1, and the Y direction indicates the “difficult magnetization axis direction” of the spontaneous magnetization. At this time, in the above-described “parallel state” and “anti-parallel state”, the spontaneous magnetization in the free layer 2 and the pinned layer 4 is stabilized along the easy magnetization axis direction (X direction). Current I flowing through word line WL during write operation

 As shown in Fig. 2, a magnetic field H along the Y direction is generated near the TMR element 1 by WL.

 Y

 To do. In addition, the current I flowing through the bit line BL causes the vicinity of the TMR element 1 along the X direction.

 BL

 The generated magnetic field H is generated. Spontaneous in the free layer 2 by these generated magnetic fields H and H

 X X Y

 Magnetization rotates. The combination of these magnetic fields H and H satisfies a predetermined condition.

 X Y

 In this case, the direction of the spontaneous magnetization is reversed.

 FIG. 3A is a graph showing the predetermined condition. In Figure 3A, the vertical axis represents current I

 WL

 The horizontal axis indicates the current I. In addition, the curve shown in Figure 3A is a “steroid curve”.

 BL

 The intercept of the steroid curve and the vertical axis' horizontal axis is +1, -I, +1,

 XO XO YO

 Is given by -I. This steroid curve is used to reverse the spontaneous magnetism in the free layer 2.

YO

 Indicates the minimum current I, 1 required. In other words, the outside of this steroid curve ("Rever

 WL BL

 If the currents I and I corresponding to the sal region ") are applied, is the TMR element 1 in the" parallel state "?

 WL BL

 To "anti-parallel state" or from "anti-parallel state" to "parallel state". That is, the data value “1” or “0” is written into the memory cell. On the other hand, the applied currents I and I

 WL B

 Force When writing data inside the steroid curve ("Retention area"), write data

L

 Is not performed.

 [0007] FIG. 3B is a graph showing the distribution of the asteroid curve described above for a plurality of memory cells. In FIG. 3B, the vertical axis represents current I, and the horizontal axis represents current I. Typically,

 WL BL

In an MRAM, a plurality of memory cells are arranged in an array, and there are variations in the characteristics of the TMR element 1 that the plurality of memory cells have. Therefore, the steroid curve group (curve group) for multiple memory cells is shown as curve C as shown in Fig. 3B. It will be distributed between max and the curve Cmin. Where the intercept of the curve Cmax is I (max),

 X

 The intercept of the curve Cmin is given by I (min) and I (min).

 Y X Y

 [0008] First, the currents I and I at the time of writing must exist at least outside the curve Cmax (Reversal region) so that writing can be performed even with respect to a shift of a plurality of memory cells.

WL BL

 The Also, other memory cells are connected to the word line WL or bit line BL selected at the time of writing. Writing to such other memory cells by the generated magnetic field H, H

 X Y

 The current I flowing through the word line WL is a bit smaller than I (min) so that no penetration occurs.

 WL X

 The current I flowing through the line BL needs to be smaller than I (min). In other words, the power

 BL Y

 If the current I, 1 does not correspond to the hatched area (write margin) in Figure 3B

WL BL

 Don't be. As the variation in characteristics of the TMR element 1 increases, the write margin decreases. In this way, MRAM requires precise control of the write current.

 As the number of memory cells increases in response to a request for further improvement in storage capacity, the variation in characteristics of the TMR element 1 can be further increased. In other words, the probability that there is a memory cell to which data is not successfully written is further increased. Such memory cells and other memory cells having defects are hereinafter referred to as “defective memory cells”. It is desirable to provide a highly reliable MRAM by reducing the effects of defective memory cells. In addition, there is a demand for a technique for improving the discriminability of data stored in a memory cell by reducing the influence of a defective memory cell. In addition, a technique that can reduce the influence of defective memory cells and improve yield is desired.

 In a general semiconductor memory device, a method for improving the yield by replacing such a defective memory cell with a specific cell in the redundancy cell array is known. Usually, a redundancy cell has the same structure as a normal memory cell. Therefore, even if a defective memory cell is replaced with a redundancy cell, the variation in characteristics of the TMR element 1 still exists. In other words, even if the repair method using the redundancy cell array is applied to the MRAM, the above-mentioned problem relating to the write failure is not essentially solved.

[0011] Further, as a means for realizing high reliability, for example, ECC (Error Correction Code) Can be considered. However, according to ECC, there is a problem that time overhead is large because error detection and correction of output data are performed.

[0012] The related technical capabilities of MRAM are disclosed in Japanese Patent Application Laid-Open No. 2004-39150. The purpose of this conventional technique is to provide a technique for improving the reliability of discrimination of data stored in the memory cell of the MRAM by eliminating the influence of the sneak path current. This MRAM has a cross-point cell array, a plurality of word lines extending in the first direction, a plurality of bit lines extending in the second direction, and a dummy extending in the second direction. A bit line and a read circuit are provided. This read circuit includes an offset removal circuit and a data discrimination circuit. The offset removal circuit is configured such that a voltage is applied between a selected word line and a selected bit line, and a voltage applied between the selected word line and a dummy bit line. A current difference signal corresponding to the difference from the offset component current flowing in the dummy bit line is generated. The data discrimination circuit discriminates the stored data stored in the selected cell interposed between the selected word line and the selected bit line based on the current difference signal.

 [0013] Japanese Patent Laid-Open No. 2002-124095 discloses a circuit that is incorporated in an image processing circuit and that repairs a defect in a storage device having a storage area having a plurality of memory cell capabilities. The defect relief circuit includes a selector and a register that stores designation information of a segment obtained by dividing a storage area into a plurality of indexes. The selector selects the index corresponding to the segment designation information included in the address signal from the register, reads the segment designation information associated with the index, and outputs the segment designation information to the storage device. Further, the semiconductor memory device disclosed in Japanese Patent Laid-Open No. 10-312340 includes an ECC circuit and a data conversion circuit for sending a conversion matrix corresponding to the selected combination of the select register power to the ECC circuit.

[0014] In addition, an apparatus having a majority circuit is disclosed in JP-A-7-105037 and JP-A-2000-163320. The processing board disclosed in Japanese Patent Application Laid-Open No. 7-105037 is provided with X processing units (X is 3 or more), a majority unit, and a processor bus that connects the processing unit and the majority unit. Each processing unit has a processor and a cache memory. The majority unit is a processor. Select one of the single units and function as an input / output interface with the outside. Japanese Laid-Open Patent Publication No. 2000-163320 discloses a memory device with a soft error countermeasure function that determines a soft error of a memory cell and selectively outputs data determined not to suffer from a soft error. This memory device has a majority circuit. The majority circuit performs a majority process on the stored contents of each of the three or more memory cells, and selects data without suffering a software error.

[0015] In addition, Japanese National Patent Publication No. 2002-502549 discloses a memory device. The memory device includes a plurality of memory elements and a selection circuit having a plurality of solid elements and connected to the memory elements. Each solid state device includes a network of thin film elements. At least one thin film element provides a giant magnetoresistance. The network has a plurality of nodes, each of which electrically connects two of the thin film elements. Of the plurality of nodes, the first and second nodes have power terminals, and among the plurality of nodes, the third and fourth nodes have outputs. The first conductor is inductively coupled to at least one thin film element and applies a magnetic field thereto.

 Disclosure of the invention

 [0016] An object of the present invention is to provide a nonvolatile semiconductor memory device using a magnetoresistive element. In particular, an object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce the influence of defective memory cells.

 Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving the discriminability of data stored in a memory cell and improving the reliability of the device.

 [0018] Still another object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving yield and reducing manufacturing cost.

In the first aspect of the present invention, the nonvolatile semiconductor memory device uses a magnetoresistive element whose resistance changes according to the direction of spontaneous magnetization that can be reversed. The nonvolatile semiconductor memory device includes a plurality of memory cells each having a magnetoresistive element, a write data processing circuit that supplies write data to be written to the plurality of memory cells to each of the plurality of memory cells, and Multiple memory cell power Read data read out And a read data processing circuit that creates output data to be output to the outside. During the write operation, the write data processing circuit supplies the same write data to n (n is an integer of 2 or more) memory cells among the plurality of memory cells. During the read operation, the read data processing circuit determines one output data based on the n read data read from each of the n memory cells. In particular, when n is an odd number, the read data processing circuit preferably determines one output data from the n read data by performing a majority operation.

[0020] In the nonvolatile semiconductor memory device according to the present invention, the n memory cells are arranged in the same memory cell array. At this time, the n memory cells are interposed between the same write word line of the plurality of write word lines and the same bit line of the plurality of bit lines. The plurality of bit lines are preferably arranged along the hard magnetization axis direction of the magnetoresistive element, and the n memory cells are preferably arranged along the same direction as the same bit line.

 In the nonvolatile semiconductor memory device according to the present invention, the n memory cells are respectively connected to n memory cell arrays different from each other among N (N is an integer equal to or larger than n) memory cell arrays. Be placed. At this time, the n memory cells are arranged at the same address in each of the n memory cell arrays.

 In this nonvolatile semiconductor memory device, the read data processing circuit has an output data determination circuit having n input terminals. Each of the n input terminals is connected to the n memory cell arrays. The output data determination circuit receives n read data from each of the n memory cell arrays, and performs a majority operation to determine one output data from the n read data.

In this nonvolatile semiconductor memory device, the read data processing circuit determines an output data having an allocation circuit connected to the N memory cell arrays and n input terminals connected to the allocation circuit. Circuit. The assignment circuit receives an assignment signal. This assignment signal indicates n memory cell arrays associated with the n input terminals among the N memory cell arrays. The allocation circuit refers to the allocation signal, and receives the n memory cell array capabilities associated with the n readings. Output the read data to each of the n input terminals. The output data determination circuit determines one output data from the n read data by performing a majority operation. This output data decision circuit sets two of the n read data to '1' and '0' in response to a control signal input from the outside, and then performs majority operation to determine n One output data may be determined from the read data. The assignment signal is preferably stored in a register connected to the assignment circuit.

 In this nonvolatile semiconductor memory device, the read data processing circuit determines an output data having an allocation circuit connected to the N memory cell arrays and N input terminals connected to the allocation circuit. Circuit. This output data determination circuit selects N input terminals and n input terminals based on a selection signal indicating the value of n. The assignment circuit receives an assignment signal. This allocation signal indicates n memory cell arrays associated with the n input terminals among the N memory cell arrays. The allocation circuit refers to the allocation signal, and outputs the n read data received by the associated n memory cell breakers to each of the n input terminals. The output data determination circuit determines one output data from the n read data by performing a majority operation. The selection signal is preferably stored in a register connected to the output data determination circuit. Also, the assignment signal is preferably stored in a register connected to the assignment circuit! /.

[0025] In a second aspect of the present invention, the nonvolatile semiconductor memory device uses a magnetoresistive element whose resistance changes according to the direction of spontaneous magnetization that can be reversed, and generates data according to the direction of spontaneous magnetization. A memory cell for storage is provided. This nonvolatile semiconductor memory device includes a plurality of bit lines, a plurality of write word lines arranged so as to cross the plurality of bit lines, and intersections of the plurality of write word lines and the plurality of bit lines. A plurality of arranged memory cells and a read data processing circuit connected to a plurality of bit lines. Among the plurality of memory cells, n (n is an integer of 2 or more) memory cells are arranged between the same write word line of the plurality of write word lines and the same bit line of the plurality of bit lines. Intervened. At this time, the read data processing circuit outputs to the outside based on n read data read from each of the n memory cells through the same bit line. Determine the output data to be output. In particular, when n is an odd number, it is preferable that the read data processing circuit determines one output data from the n read data by performing a majority operation. The plurality of bit lines are preferably arranged along the direction of the hard magnetization axis of the magnetoresistive element, and the n memory cells are preferably arranged along the same direction as the same bit line.

 According to a third aspect of the present invention, a nonvolatile semiconductor memory device crosses a memory cell array in which a plurality of group cells are arranged in a matrix, a plurality of bit lines, and the plurality of bit lines. And a plurality of write word lines arranged to do so. Each of the plurality of group cells includes n (n is an integer of 2 or more) memory cells. Each of the n memory cells has a magnetoresistive element. In each group cell, the n memory cells are interposed between the same write word line of the plurality of write word lines and the same bit line of the plurality of bit lines. Further, it is preferable that the plurality of bit lines are arranged along the difficult magnetic axis direction of the magnetoresistive element, and the n memory cells are arranged along the same direction as the same bit line. . The nonvolatile semiconductor memory device further includes a read data processing circuit connected to the plurality of bit lines. This read data processing circuit determines one output data by performing a majority operation based on n read data read from n memory cells via the same bit line.

 [0027] According to the nonvolatile semiconductor memory device of the present invention, the influence of defective memory cells is reduced.

 According to the nonvolatile semiconductor memory device of the present invention, the discriminability of data stored in the memory cell is improved, and the reliability of the device is improved.

[0029] According to the nonvolatile semiconductor memory device of the present invention, the yield is improved and the manufacturing cost is reduced.

 Brief Description of Drawings

FIG. 1A is a conceptual diagram showing a configuration of a general TMR element.

 FIG. 1B is a conceptual diagram showing a configuration of a general TMR element.

[FIG. 2] FIG. 2 is a diagram for explaining a write principle for a memory cell having a TMR element. FIG.

 FIG. 3A is a graph showing a steroid curve for a certain memory cell.

[FIG. 3B] FIG. 3B is a graph showing the distribution of asteroid curves for a plurality of memory cells.

 FIG. 4 is a block diagram showing a configuration of a memory cell array according to the embodiment of the present invention.

 FIG. 5 is a block diagram showing a configuration of the MRAM according to the exemplary embodiment of the present invention.

FIG. 6 is a conceptual diagram for explaining an operation of the MRAM according to the exemplary embodiment of the present invention.

 FIG. 7 is a block diagram showing a configuration of a read data processing circuit according to the first embodiment of the present invention.

 FIG. 8A is a circuit diagram showing an example of a three-majority logic circuit.

[8B] FIG. 8B is a circuit diagram showing an example of a five-majority logic circuit.

 FIG. 9 is a timing chart showing a read operation according to the first embodiment of the present invention.

 FIG. 10 is a block diagram showing a configuration of a write data processing circuit according to the first embodiment of the present invention.

 [FIG. 11] FIG. 11 is a graph showing the relationship between the fail rate and the non-defective chip rate.

 FIG. 12 is a block diagram showing a configuration of a read data processing circuit according to a second embodiment of the present invention.

 FIG. 13A is a circuit diagram showing an example of an IZO allocation circuit.

FIG. 13B is a circuit diagram showing an example of a 4-1 selector.

 FIG. 14 is a block diagram showing a configuration of a read data processing circuit according to a second embodiment of the present invention.

[15A] FIG. 15A is a circuit diagram showing an example of an input data determination circuit according to the second embodiment of the present invention.

 FIG. 15B is a circuit diagram showing an example of a coincidence detection circuit.

FIG. 16 shows a configuration of a read data processing circuit according to the second embodiment of the present invention. It is a block diagram which shows the modification of.

 FIG. 17 is a block diagram showing a configuration of a read data processing circuit according to a third embodiment of the present invention.

 FIG. 18 is a block diagram showing a configuration of an output data determination circuit according to the third embodiment of the present invention.

 FIG. 19 is a block diagram showing a configuration of an MRAM according to a fourth exemplary embodiment of the present invention.

 FIG. 20 is a timing chart showing a read operation according to the fourth embodiment of the present invention.

 BEST MODE FOR CARRYING OUT THE INVENTION

 A nonvolatile semiconductor memory device according to the present invention will be described with reference to the accompanying drawings. This nonvolatile semiconductor memory device is a magnetic random access memory (MRAM) using a magnetoresistive element.

 FIG. 4 is a block diagram showing a part of the configuration of the MRAM according to the embodiment of the present invention. The MRAM 200 includes a memory cell array 100 in which a plurality of memory cells 10 are arranged in an array, a plurality of write word lines 21, a plurality of read word lines 22, and a plurality of bit lines 31. The plurality of write word lines 21 and the plurality of read word lines 22 are arranged along the X direction in the figure. The plurality of bit lines 31 are arranged along the Y direction in the figure so as to intersect the word lines (21, 22).

 Each of the plurality of memory cells 10 is provided corresponding to the intersection of the write word line 21, the read word line 22, and the bit line 31. The plurality of memory cells 10 include a reference cell 10r used for reading data. Each memory cell 10 includes the magnetoresistive element (TMR element) 1 and the MOS transistor 5 shown in FIGS. 1A and 1B. The gate of the MOS transistor 5 is connected to the read word line 22. One end of the TMR element 1 is connected to the bit line 31, and the other end is connected to one of the source / drain of the MOS transistor 5.

In each memory cell 10, the TMR element 1 is interposed between the write word line 21 and the bit line 31. In each memory cell 10, the TMR element 1 is in the free layer 2. It is arranged so that the “easy magnetic axis direction” of the spontaneous magnetic axis is along the X direction. At this time, the Y direction indicates the “difficult magnetic axis direction” of the spontaneous magnetization in the free layer 2. In the above-mentioned “parallel state” and “anti-parallel state”, the spontaneous magnetic field に お け る in the free layer 2 and the pinned layer 4 is stabilized along the X direction. Further, as described above, the write word line 21 is arranged along the X direction and generates a magnetic field H along the Y direction (difficult magnetic axis direction). On the other hand, the bit line 31 is

 Y

 Arranged along the Y direction, generates a magnetic field H along the X direction (easy magnetization axis direction)

 X

 Make it. When a current is passed through the write word line 21 and the bit line 31, the generated magnetic fields H and H

 X Y

 Therefore, the spontaneous magnetic field に お け る in the free layer 2 rotates clockwise or counterclockwise. When the predetermined condition shown in FIGS. 3A and 3B is satisfied, the direction of the spontaneous magnetic field in the free layer 2 is reversed and set in the + X direction or the X direction.

 [0035] The MRAM 200 further includes an X-side selector 23, an X-side current termination circuit 24, an X-side current source circuit 25, a Y-side selector 33, a Y-side current termination circuit 34, a Y-side current source circuit 35, and a read current load circuit. A path 36 and a sense amplifier 40 are provided.

 The X-side selector 23 selects a selected write word line from the plurality of write word lines 21 during a write operation, and selects a selected read word line from the plurality of read word lines 22 during a read operation. The X-side current termination circuit 24 terminates the write word line 21. The X-side current source circuit 25 is a current source that supplies a predetermined current to the selected write word line during a write operation. The Y-side selector 33 selects a selected bit line from the plurality of bit lines 31. The Y side current termination circuit 34 terminates the bit line 31. The Y-side current source circuit 35 is a current source that supplies a predetermined current to the selected bit line during a write operation. The read current load circuit 36 is a constant current source that supplies a constant current to the bit line 3 lr connected to the selected bit line and the reference cell 10r during the read operation.

Data is written into the memory cell 10 in a certain memory cell array 100 as follows. First, “address data” indicating a target cell to which data is written and “write data DW” indicating data to be written are supplied to a controller (not shown) that controls reading and writing in the memory cell array 100. In response to the control signal from the controller, the X-side selector 23 selects the selected write word line, and the X-side current source circuit 25 supplies a predetermined current to the selected write word line. Also conte mouth In response to the control signal, the Y-side selector 33 selects the selected bit line, and the Y-side current source circuit 35 supplies a predetermined current to the selected bit line. As a result, the spontaneous magnetization is reversed in the free layer 2 of the TMR element 1 sandwiched between the selective write side line and the selected bit line. That is, the write data DW is written to the memory cell 10 specified by the address data.

 [0038] Here, if the supplied current does not satisfy the “write margin” (see FIG. 3B)! / If the desired write data DW is not written to the target cell, Undesirable data is written to the memory cell. That is, a write error occurs. In this way, the memory cell 10 in which the desired write data DW is not easily written, and the memory cell 10 that is easily affected by the write operation to other memory cells, is the above-mentioned “defective memory cell”.

 In addition, reading of data from the memory cell 10 in a certain memory cell array 100 is performed as follows. First, “address data” indicating a target cell from which data is read is supplied to the above-described controller (not shown). Based on the control signal from this controller, the X-side selector 23 selects the selected read word line. As a result, the MOS transistor 5 of the memory cell 10 and the reference cell lOr connected to the selected read word line is turned ON. The Y-side selector 33 selects the selected bit line according to the control signal of the controller. The read current load circuit 36 supplies a constant current to the selected bit line and the bit line 3 lr connected to the reference cell 10r. As a result, the voltage of the selected bit line becomes a “read voltage” corresponding to the resistance value of the TMR element 1 of the target cell specified by the selected read word line and the selected bit line. The voltage of the bit line 31r is a predetermined “reference voltage” corresponding to the resistance value of the TMR element 1 of the reference cell 10r.

The sense amplifier 40 detects the resistance value of the TMR element 1 of the target cell, that is, the data value stored in the target cell by comparing the read voltage with the reference voltage. For example, if the read voltage is higher than the reference voltage, it is determined that the data value “1” is stored in the target cell. If the read voltage is lower than the reference voltage, the data value “0” is stored in the target cell. It is determined that Read in this way The read “read data DR” is output to the I / O of the memory cell array 100.

FIG. 5 is a block diagram showing a configuration of MRAM 200 according to the embodiment of the present invention.

 The MRAM 200 includes a plurality of memory cell arrays 100 and a data processing circuit 300 connected to the plurality of memory cell arrays 100. The data processing circuit 300 includes a write data processing circuit 400 and a read data processing circuit 500 connected to the plurality of memory cell arrays 100.

[0042] For example, the MRAM 200 has N (N is an integer of 2 or more) memory cell arrays 100-0 to 10- (N-l). Each of these memory cell arrays 100-0 to 100- (N-1) is connected to the data processing circuit 300 via IZO-0 to IZO- (N-1). Memory memory array 100—0 to: L00— (N-1) is supplied with write data DW0 to DW (N—1) via IZO—0 to lZO— (Ν—1), respectively. The Memory cell array 100—0 ~: From LOO— (N—1), read data 01 ^ 0 to 01 ^^ via I / O—0 to l / O— (N—1) respectively. —1) is output.

The write data processing circuit 400 receives input data Din and address data XADD and YADD specifying the write target cell from the outside. The write data processing circuit 400 specifies the write data DW0 to DW (N—1) to be supplied to each of the memory cell arrays 100—0 to 100— (N—1) from the input data Din. . Then, the write data processing circuit 400 applies the write data DW0 to DW (N—1) to each of the memory cell arrays 100-0 to LOO— (N—1) together with the address data XADD and YADD. And supply.

 The read data processing circuit 500 receives address data XA DD and YADD that specify a cell to be read from the outside, and receives the address data XADD and YADD from the memory cell array 100—0 to: LOO— (N—1). Supply for each. The read data processing circuit 500 receives the read data DR0 to DR (N—1) output from each of the memory cell arrays 100-0 to 100- (N−1) and receives the read data DR0 to DR. Based on (N-1), output 1 or more output data Dout to the outside.

FIG. 6 is a conceptual diagram for explaining the operation of MRAM 200 according to the embodiment of the present invention. In the embodiment of the present invention, the plurality of memory cell arrays 100 includes one or more. The gnole is converted into a gnole. One such gnolepe is referred to below as the “Gnorepe Array GA”. For example, the group array GA-0 is “a” memory cell array 100 (A

 0

~ A) Force composed. Similarly, the group array GA-1 has “b” memory cell arrays.

1 Oa

 The group array GA-2 consists of “c,” memory cell arrays.

 11 lb

 100 (A to A) force composed. At this time, the number of the plurality of memory cell arrays 100 described above

 21 2c

 N is represented by N = a + b + c + "'. In each of the plurality of memory cell arrays 100 constituting each group array GA, reading / writing is performed on a predetermined memory cell 10 (target cell). A plurality of target cells belonging to each group array GA is hereinafter referred to as “group cell GC”. The plurality of IZOs corresponding to each group array GA is hereinafter referred to as “GlZO (group lZO)”.

 [0046] According to the present invention, these group array GA and group cell GC are handled as one unit. For example, a group cell GC has η (η is an integer not less than 2 and not more than メ モ リ) memory cells 10. The above data processing circuit 300 uses this group cell GC as one memory cell. Treat like. Specifically, during the write operation, the write data processing circuit 400 supplies the same write data DW to a certain group cell GC. Further, during the read operation, the read data processing circuit 500 is based on η read data DR read from each of η memory cells (target cells) 10 constituting a certain group cell GC. Determine one output data Dout. Therefore, when the above N memory cell arrays 100 (100—0-100— (N—1)) are classified into M (M is an integer of 2 or more) group array GA, the read data processing circuit From 500, only M output data Dout are output.

 [0047] In particular, when n is an odd number (that is, n is an odd number not less than 3 and not more than N), the read data processing circuit 500 performs the majority operation to obtain the n read data DR power. It is preferable to determine one output data Dout.

[0048] During the write operation, the same write data DW is supplied to the group cell GC. However, when “bad memory cells” exist, a write error may occur as described above. For example, the same write data DW may not be written correctly to any of the n memory cells 10 that make up the group cell GC. is there. There is a possibility of a “deviation” between the write data DW and the stored data actually stored in the memory cell 10. For this reason, it is meaningful to determine one final output data Dout from n read data DR by a method such as majority voting. That is, the influence of the defective memory cell is reduced, and the discriminability of data stored in the memory cell 10 is improved.

 Hereinafter, the configuration / operation of the MRAM 200 according to the present invention will be described in more detail.

 [0050] (First embodiment)

 FIG. 7 is a block diagram schematically showing the configuration of the read data processing circuit 500A according to the first embodiment of the present invention. Here, as an example, the case where the MRAM 200 includes 16 memory cell arrays 100-0 to 100-15 (N = 16) is shown. Each of these memory cell arrays 100-0 to 100-15 is connected to the read data processing circuit 500A via I / O-0 to l / O-15. At this time, the memory cell arrays 100-0 to 100-15 output the read data DR0 to DR15 via the I / O-0 to 1 / O-15, respectively. In the figure, the numbers in circles indicate IZO numbers.

 [0051] Further, as an example, it is assumed that these 16 memory cell arrays are classified into 100 group arrays GA-0 to GA-3 (M = 4). For example, the group array GA-0 is composed of three memory cell arrays 100-0 to: LOO-2 (Α to Α) force (η = 3), and GlZO-0 is I

 01 03

 It is composed of ZO—0 to lZO—2. Group array GA-1 is composed of three memory cell arrays 100-3 to L00-5 (—) force (n = 3), GlZO-1 is ΐΖθ 3

 11 ~ Α

 13

 ~ LZO—It consists of 5. Group array GA-2 is composed of five memory cell arrays 1 00-6 to: L00-10 (Α21 to Α25) force (η = 5), GlZO-2 is I / O-6 to lZ

Ο—It consists of ten. Group array GA-3 has 5 memory cell arrays 100 11 to 100-15 (Α),

 31 to Α 35) composed of force (n = 5 GlZO—3 is IZO—11 to ΙΖ

Ο—consists of 15

In the present embodiment, η memory cells 10 constituting a certain group cell GC are arranged in η memory cell arrays 100 different from each other. For example, the group cell GC corresponding to the double array GA-0 is composed of three memory cells 10, and each of the three memory cells 10 is assigned to each of the three memory cell arrays A to A. One by one. Here, it is preferable that the three memory cells 10 are arranged at the same address in each of the three memory cell arrays A to A.

 01 03

 As described above, the read data processing circuit 500A determines one output data Dout based on n read data DR read from a certain group cell GC. Therefore, this data processing circuit 500A has four output data decision circuits 510-0 to 510-3 for each of the four group arrays GA-0 to GA-3. Yes.

 [0054] For example, the output data determination circuit 510-0 includes three input terminals T to T and one output terminal.

 01 03

 The three input terminals Τ to Τ are those of the memory cell arrays A to A.

 01 03 01 03 Connected to each other. Read data DR0 to 0 scale 2 output from group array GA-0 is input to each of three input terminals D to T via 170-0 to 10-2.

 01 03

 Is done. The output data determination circuit 510-0 determines one output data Dout-0 based on the three read data DR0 to DR2. Here, n is an odd number (n = 3), and the output data decision circuit 510-0 is exemplified by a “majority logic circuit” that executes a majority decision operation.

 FIG. 8A is a circuit diagram showing an example of a three-majority logic circuit as the output data determination circuit 510-0. As shown in FIG. 8A, this three-majority logic circuit has input terminals T to T and an output terminal.

 01 03 Prepare the power terminal OUT and NAND511a ~ 511d, and execute majority operation with this configuration. In other words, the value (“0” or “1”) indicated by two or more of the three input read data DR0 to DR2 is output as output data Dout-0 from the output terminal OUT.

 [0056] Referring also to FIG. 7, the output data determination circuit 510-2 includes five input terminals T to T and 1

 21 There are 25 output terminals, and the five input terminals Τ to Τ are connected to the memory cell array A.

 21 25 21

Connected to each of ~ A. Reading output from group array GA-2

twenty five

 Data DR6 to DR10 are the five input terminals T to T via lZO-6 to tZO-10

21 25 respectively. The output data determination circuit 510-2 determines one output data Dout-2 based on the five read data DR6 to DR10. Here, n is an odd number (n = 5), and the output data determination circuit 510-2 is exemplified by a “majority logic circuit” that executes a majority operation. FIG. 8B is a circuit diagram showing an example of a five-majority logic circuit as the output data determination circuit 510-2. As shown in FIG. 8B, the five majority logic circuit has input terminals T to T, output terminals,

 21 25 Power terminal OUT, NAND511e to 511q, and OR512 are provided, and the majority operation is executed with this configuration. In other words, the value indicated by three or more of the five input read data DR6 to DR10 (“0” or “1”) is output as output data Dout-2 from the 1S output terminal OUT.

 [0058] Similar to the output data determination circuit 510-0, the output data determination circuit 510-1 includes three input terminals T to T and one output terminal, and the three input terminals 〜 to Τ

 11 13 11 13 Connected to each of the memory cell arrays A to A. This output data decision circuit 51

 11 13

 0-1 determines the output data Dout-1 from the three read data DR3 to DR5 by executing the majority operation (see FIG. 8A). Similarly to the output data decision circuit 510-2, the output data decision circuit 510-3 has five input terminals T to T and one output terminal.

 31 35

 The five input terminals Τ to Τ are those of the memory cell arrays A to A.

 31 35 31 35 Connected to each. The output data determination circuit 510-3 determines one output data Dout-3 from the five read data DR11 to DR15 by executing a majority operation (see FIG. 8B).

 The output data Dout-0 to Dout-3 finally determined by each output data determination circuit 510 as described above are output to the outside via the selector 520. The output data Dout (Dout-0 to Dout-3) is output simultaneously or serially. Thus, in this embodiment, four output data Dout-0 to Dout-3 are output corresponding to four groups lZO (GlZO-0 to GlZO3).

Next, an example of the read operation according to the present embodiment will be described with reference to FIGS. 4 and 7 together with FIG. Here, as an example, a case where the output data Dout is output from the group array GA-0 through GI / O-0 is shown. At time tO, the signal ZRE force changes to the Low level that is input to the read current load circuit 36 of each memory cell array (100-0 to: L00-2). Thereby, each memory cell array 100 changes to the read mode. Subsequently, address signals XADD and YA DD for specifying the group cell GC to be read are input. Here, the three target cells that make up the group cell GC They are arranged at the same address in the memory cell array.

 Next, at time tl, the bit line activation signal RBL is input to the Y-side selector 33, and the bit line 31 corresponding to the address signal YADD is activated as the selected bit line. At time t2, the word line activation signal RWL is input to the X-side selector 23, and the read word line 22 corresponding to the address signal XADD is activated as the selected word line. As a result, a read current flows through the target cell 10 specified by the selected word line and the selected bit line. At the same time, a read current flows also in the reference cell 10r. Next, at time t3, the sense amplifier activation signal SAEN becomes High level, and the sense amplifier 40 compares the read voltage with the reference voltage. Thereby, the data stored in each memory cell 10 constituting the group cell G C is detected.

 [0062] At time t4, the data detected as described above is output from each of IZO-0 to IZO-2 as read data DR0 to DR2. The output data determination circuit 510 — 0 determines one output data Dout from the read data DR0 to DR2 by executing a majority operation. In FIG. 9, the solid line shows the case where DR0 to DR3 are all “1”. In this case, the output data determination circuit 510-0 outputs “1” as the output data Dout. In FIG. 9, the broken line indicates a case where DR0 is “1” and DR1 and DR2 are “0”. In this case, the output data determination circuit 510-0 outputs “0” as the output data Dout. The read operation ends at time t5. The read operation is the same for other group arrays GA.

 [0063] Next, a description will be given regarding writing. FIG. 10 is a block diagram schematically showing the configuration of the write data processing circuit 400A according to the present embodiment. Each of the memory cell arrays 10 0-0 to L00-15 is connected to the write data processing circuit 400A via I / O-0 to l / O-15. At this time, the write data DW0 to DW15 are supplied to the memory cell arrays 100-0 to L00-15 via I / O-0 to l / O-15, respectively.

The write data processing circuit 400A includes a distribution circuit 410, and the distribution circuit 410 is connected to GIZO-0 to GIZO-3. For example, when 4-bit input data Di n (Din—0 to Din—3) is written, this distribution circuit uses data Din—0 to Din— Each of 3 is output to each of GlZO-0 to GlZO-3. As a result, for example, the write data (DW0 to DW3) supplied to the three memory cell arrays 100-0 to L00-2 constituting the group array GA-0 become the same data Din-0. . That is, the write data processing circuit 400A supplies the same write data DW to each of the n memory cell arrays 100 constituting a certain group array GA. As described above, if there is a “bad memory cell” in the memory cell array 100, a write error may occur and the stored data power stored in the memory cell 10 may not match the write data DW. .

 [0065] The effects of MRAM 200 according to the present embodiment described above are as follows.

 [0066] According to the present embodiment, during a write operation, the same write data DW is supplied to a certain group array GA, and the same data is stored in n memory cells 10 constituting the group cell GC. To be controlled. However, write errors may occur due to the presence of defective memory cells. During the read operation, n read data DR output from the group cell GC belonging to the group array GA is input to a certain output data determination circuit 510. The output data determination circuit 510 determines one output data Dout based on the n read data DR. Specifically, n is represented by 2k + l (k is a natural number), and the output data determination circuit 510 determines k + 1 as a value (“0” or “1”) indicated by one or more read data DR. Adopted as output data Dout. In other words, the output data determination circuit 510 performs a majority operation.

[0067] Therefore, when the majority operation is performed on the three read data DRs, even if one of the three memory cells 10 is a defective memory cell, if the remaining memory cells 10 are normal, Data stored in the group cell GC can be read accurately. In addition, when a majority operation is performed on five read data DRs, even if two of the five memory cells 10 are defective, if the remaining memory cells 10 are normal, the group cell GC It becomes possible to accurately read out the data stored in. In general, when a majority operation is performed on n (n = 2k + 1) read data DR, even if k out of n memory cells 10 are defective memory cells, the remaining memory cells 10 Is normal If so, the data stored in the group cell GC can be read accurately. Therefore, according to the MRAM 200 according to the present invention, the influence of defective memory cells is reduced. In addition, the discriminability of data stored in the memory cell 10 is improved, and the reliability of the device is improved.

The probability that a certain memory cell 10 is a defective memory cell is referred to as “failure rate p”. For example, a failure rate p of 0.1% (p = 10 ^_3 ) is equivalent to a 1K byte defect in 1M byte. At this time, the probability P that the output data Dout calculated from the three read data DR data is correct is given by P = (1-p) ³ + 3p (l-p) ² . 5 readings

 3 3

Outgoing data DR force Probable output data Dout Probability P is P = (l -p) ⁵ +

 5 5

5p (l—p) ⁴ + 10p ² (l—p) ³ . For example, when the failure rate p is 1% (p = ^10_2 ), P is 99.970% and P is 99.999%.

 3 5

FIG. 11 is a graph showing the relationship between the fail rate and the chip non-defective rate. In Fig. 11, the vertical axis shows the chip non-defective rate, the horizontal axis shows the fail rate, and the case where various majority logic circuits are applied is shown. In the figure, each of reference numerals “110” to “1510” indicates a case where 1 majority logic circuit (no majority vote) to 15 majority logic circuit is applied. As is clear from Fig. 11, the failure rate allowed to obtain good products can be increased as the number of data used in the majority decision increases. For example, 3 majority logic circuit (indicated by reference numeral "310") when applied, the fail rate p is allowed to 10_ ³ extent. 5 If the majority logic circuit is applied (indicated by reference numeral "510"), Hue I le rate p is allowed until ² about 10_. As described above, according to the MRAM 200 according to the present invention, the yield rate of chips is dramatically improved and the yield is improved. Therefore, the manufacturing cost is reduced.

 Furthermore, the MRAM 200 according to the present invention does not limit the configuration of the memory cell array 100 (see FIG. 4). Therefore, there is an advantage that the above-described effect can be obtained with only a simple peripheral circuit without affecting the degree of integration. Another advantage is that it can operate faster than ECC.

 [0071] (Second Embodiment)

FIG. 12 shows the configuration of the read data processing circuit 500B according to the second embodiment of the present invention. FIG. Again, as an example, the case of N = 16 is shown. That is, the read data processing circuit 500B is connected to the memory cell array 100-0 to LOO-15 via each of the I / O-0 to l / O-15. In the figure, the numbers in circles indicate the IZO numbers. Further, in the memory cell array 100, the middle force in FIG. 12 is also omitted. In FIG. 12, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

 The read data processing circuit 500 備 え includes output data determination circuits 510-0 to 510-3 and a selector 520, as in the first embodiment. Each of these output data determination circuits (majority logic circuits) 510-0 to 510-3 determines output data Dout-0 to Dout-3 based on η pieces of read data DR.

 In the present embodiment, the correspondence between a plurality of IZOs and output data determination circuit 510 can be set flexibly. For example, the output data decision circuit 510-0 has an input terminal 端子

 01

Τ η (η = 3), but their input terminals Τ Τ Τ are 16 lZO (lZO— 0

03 01 03

 ~ LZO—Associating with any three of 15). Therefore, the read data processing circuit 500 Β further includes a ΙΖΟ assignment circuit 530 interposed between the plurality of ΙΖΟ and the output data determination circuit 510. That is, the ΙΖΟ allocation circuit 530 is connected to each of the output data determination circuits 510-0 to 510-3. On the other hand, this ΙΖΟ allocation circuit 530 is connected to each of the memory cell arrays 100-0 to 100-15 via each of I / O-0 to l / O-15, and read data DR0 to DR15. Receive each of the

 [0074] This IZO allocation circuit 530 is an "allocation" that specifies the correspondence between ΙΖΟ and input terminal Τ.

 1]

 It also receives external signals from the guess signal ASGN. Where the value of i is 0-3 and the value of j is l-n

 1]

 is there. For example, when ASGN = 5, ASGN = 3, ASGN = 8, output data is determined

 01 02 03

 The input terminals T, T, and T of circuit 510-0 are IZO-5, lZO-3, and lZO-8, respectively.

 01 02 03

 Is associated with. That is, these associated ΙΖΟ-5, I / O -3, and ΙΖΟ-8 constitute GIZO-0. In this way, the assignment signal ASGN has n input terminals T to T.

 n memory cell arrays associated with ij il are shown. As shown in Figure 12, the assignment signal m

For example, ASGN is stored in the external register 600 connected to the IZO allocation circuit 530. It is paid. Therefore, it is possible to arbitrarily set the contents indicated by the assigned signal ASGN. That is, the contents indicated by the allocation signal ASGN are variable.

 The IZO allocation circuit 530 refers to the allocation signal ASGN, and outputs each of the read data DR0 to DR15 that has received a plurality of I / O outputs to the corresponding input terminal T. For example, the IZO allocation circuit 530 outputs read data DR5, DR3, and DR8 received from the memory cell arrays 100-5, 100-3, and 100-8 to the input terminals Τ, Τ, and そ れ ぞ れ, respectively.

 01 02 03

 FIG. 13A is a circuit diagram showing an example of the IZO allocation circuit 530. This I / O allocation circuit 530 is a terminal to which read data DR0 to DR15 is input, a terminal to which 4-bit allocation signals ASGN [0] to ASGN [3] are input, and an input terminal of the output data determination circuit 510 It has a terminal connected to T. In addition, the IZO allocation circuit 530 includes 4-1 selectors 531a to 531e. FIG. 13B is a circuit diagram showing an example of one 4-1 selector 531. The 4-1 selector 531 includes terminals IN 0 to IN 3 to which four read data DR are input, terminals SEL 0 and SEL 1 to which two bits of the assignment signal ASGN are input, and an output terminal OUT. The 4-1 selector 531 includes AND532a to 532d, OR 533a to 533c, and inverters 534a and 534b. With such a configuration, the lZO allocation circuit 530 reads the read data DR0 to DR0 based on the value indicated by the allocation signal ASGN.

One of DR15 can be output to input terminal T. For example, the assignment signal AS

If GN = 3, ie ASGN [0] = '0, ASGN [1] =' 0, ASGN [2] = 'l

02

 When ', ASGN [3] =' 1 ', read data DR3 is output to input terminal T.

 02

 The read operation in each memory cell array 100 is the same as that in the first embodiment (see FIG. 9). Accordingly, the read data processing circuit 500B receives the read data DR0 to DR15 from each of the memory cell arrays 100-0 to 100-15. Based on the assignment signal ASGN, the I / O assignment circuit 530 outputs predetermined n pieces of read data DR among the read data DR0 to DR15 to the corresponding one output data determination circuit 510. The output data determination circuit 510 determines one output data Dout as in the first embodiment.

The effect of this read data processing circuit 500B is as follows. In the wafer It can be considered that the yield is high, the memory cell array 100 is low, the yield is low, and the memory cell array 100 is mixed. In other words, it is conceivable that there is a yield distribution in the wafer. In this case, if the read data DR output from the memory cell array 100 having a relatively low yield is concentrated on the same output data determination circuit 510, the probability that accurate output data Dout is obtained decreases. That is, the chip non-defective rate decreases. According to this embodiment, the correspondence between IZO and output data determination circuit 510 can be flexibly set by assignment signal ASGN. In other words, it is possible to set the combination of ιΖο that constitutes G ιΖο so that the reliability of the chip is improved. Each memory cell array

By measuring the yield of 100 and setting the content of the allocation signal ASGN based on the measurement result, the number of chips to be rescued is further increased. Therefore, the chip non-defective rate is further improved and the manufacturing cost is further reduced.

Next, a configuration related to writing will be described. FIG. 14 is a block diagram schematically showing the configuration of the write data processing circuit 400Β according to the present embodiment. The write data processing circuit 400Β includes input data determination circuits 430-0 to 430-15 connected to ΙΖΟ-0 to 15-15, respectively. Each input data determination circuit 430 receives input data Din (Din—0 to Din—3) from the outside and the allocation signal ASGN from the register 600.

 FIG. 15A is a circuit diagram showing a configuration example of one input data determination circuit 430. The input data determination circuit 430 has 16 coincidence detection circuits 431a to 431p. The coincidence detection circuits 431a to 431p receive a 4-bit signal “I / O number signal NUM”. This IZO number signal NUM indicates the number of IΖΟ to which this input data decision circuit 430 is connected. For example, the IZO number signal NUM indicating “3” is input to the input data determination circuit 430-3 connected to ΙΖΟ-3. Each bit of the IZO number signal NUM is incorporated in the circuit in advance by the power supply potential Vdd and the ground potential Gnd.

In addition, each of the 16 match detection circuits 431a to 431p is input with each of 16 types of assigned signals ASGN. The coincidence detection circuits 431a to 431c are connected to AND433a via OR432a, and the input assignment signal ASGN is GlZO-0. (I = 0). The coincidence detection circuits 431d to 431f are connected to AND4 33b via OR432b, and the input assignment signal ASGN corresponds to GIZO-1 (i = l). The coincidence detection circuits 431g to 431k are connected to AND433c via NOR432c, 432d, and NAND432e, and the input assignment signal ASGN is GlZ

Corresponds to O-2 (i = 2). The coincidence detection circuits 4311 to 431p are connected to AND433d via NOR432f, 432g, and NAND432h, and the input assignment signal ASGN corresponds to GIZO-3 (i = 3). Ij for each of AND433a to 433d

 Of the input data Din, data Din-0 to Din-3 are input. The outputs of AND 433a to 433d are connected to each lZ0 via NOR433e, 433f, and NAND433g.

 FIG. 15B is a circuit diagram showing an example of the coincidence detection circuit 431. The coincidence detection circuit 431 includes E XNOR 435a to 435d, NAND 436a, 436b, and NOR437. With this configuration, the match detection circuit 431 compares the input 4-bit IZO number signal NUM [0] to NUM [3] with the 4-bit allocation signal ASGN [0] to ASGN [3]. I do. When the I ZO number signal NUM and the assigned signal ASGN match, this coincidence detection circuit 431 outputs “1”.

 For example, the input data determination circuit 430-3 is connected to the IZO-3 corresponding to GIZO-0 in the above example. Therefore, the IΖΟnumber signal NUM input to the input data determination circuit 430-3 indicates the value “3”. On the other hand, in the above example, the assigned signal ASGN indicating the value “3” is ASGN. Therefore, the coincidence detection circuit 431b

 ij 02

A match between the signal NUM and the assigned signal ASGN is detected, and “1” is input to AND433a. Therefore, the data Din-0 of the input data Din is output to 書 き 込 み θ-3 as the write data DW. Similarly, the same data Din-0 is output as write data DW to 170-5 and 10-0-8. That is, the same write data DW is supplied to the IZO associated with the same GIZO by the assignment signal ASGN. In this way, the write data processing circuit 400Β can supply the same write data DW to each of the n memory cell arrays 100 associated with the same group array GA by the assignment signal ASGN. FIG. 16 is a block diagram showing a modification of read data processing circuit 500B according to the present embodiment. In FIG. 16, the same components as those shown in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In this modification, optional control signals MAJ 5-0 and MAJ5-1 are externally input to the output data determining circuits 510-0 and 510-3, respectively.

 [0085] When control signal MAJ 5—0 is set to low level, output data decision circuit 510-2 connects two of five input terminals T to T to power supply potential Vdd and ground potential GND.

 21 25

 To do. In other words, in response to the control signal MAJ5_0, the output data determination circuit 510-2 sets two of the five input read data DR to “1” and “0”. Thereafter, the output data determination circuit 510-2 determines one output data Dout by performing a majority operation. This is equivalent to the output data determination circuit 510-2 determining one output data Dout from only three pieces of read data DR (three majority operation). The output data decision circuit 510-3 performs the same operation in response to the control signal MAJ5-1.

[0086] For example, among the five input terminals T to T, the input terminal Τ and the input power supply potential Vdd and the doubler

 21 25 24 25

 Suppose that it is connected to the ground potential GND. At this time, the memory cell array 100 having a very low yield is connected to the input terminal T by the assignment signal ASGN or the assignment signal ASGN.

 It can be associated with 24 25 24 or the input terminal τ. This ensures accurate output data

 twenty five

 A decrease in the probability of obtaining Dout is prevented.

[0087] As described above, according to the MRAM 200 according to the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment. In other words, the correspondence between IZO and output data decision circuit 510 is flexibly set by the assignment signal ASGN.

 ij

 Can. This prevents the read data DR force output from the memory cell array 100 having a relatively low yield from being concentrated on one output data determination circuit 510. Therefore, the probability that accurate output data Dout is obtained becomes higher. That is, the discriminability of the data stored in the memory cell 10 is further improved, and the reliability of the device is further improved. Further, the chip non-defective rate is further improved, and the manufacturing cost is further reduced.

[0088] (Third embodiment)

FIG. 17 shows the configuration of a read data processing circuit 500C according to the third embodiment of the present invention. FIG. Again, as an example, the case of N = 16 is shown. That is, the read data processing circuit 500C is connected to the memory cell array 100-0 to LOO-15 via each of the I / O-0 to l / O-15. In the figure, the numbers in circles indicate the IZO numbers. Further, in the memory cell array 100, the intermediate force in FIG. 17 is also omitted. In FIG. 17, the same reference numerals are given to the same components as those in the second embodiment, and the description thereof will be omitted as appropriate.

The read data processing circuit 500C includes a ΙΖΟ allocation circuit 530, at least one output data determination circuit 540, and a selector 520. This ΙΖΟ allocation circuit 530 is the same as that in the second embodiment, and flexibly sets the correspondence between a plurality of ΙΖΟ and the output data determination circuit 540. In other words, the ΙΖΟ assignment circuit 530 assigns a certain input terminal が included in a certain output data decision circuit 540 based on the assignment signal ASGN stored in the register 600 out of 16 lZO (lZO—0 to ΙΖΟ—15). Correlate to either of these. The configuration of the ΙΖΟ allocation circuit 530 is the same as the configuration shown in FIGS. 13A and 13B.

 In this embodiment, an output data determination circuit 540 determines one output data Dout from a designated number of read data DR. Here, the number of read data DR used is not fixed but variable. That is, when the output data determination circuit 540 performs a majority operation, the number of read data DR used for the majority operation, that is, the above-described value n is not fixed and is variable. Alternatively, the output data determination circuit 540 may be set so as not to perform majority operation. The number n of read data DR to be used is specified by a logic selection signal LSEL input from the outside. As shown in FIG. 17, the logic selection signal LSEL is stored in the external register 700 connected to the output data determination circuit 540, for example. By changing the contents of the logic selection signal LSEL stored in the external register 700, each output data determination circuit 540 can change the above-described value n.

[0091] The number n of read data DR used for the majority operation can be set to a maximum of N. Therefore, each of the output data determination circuits 540 according to the present embodiment has N input terminals T and can receive a maximum of N read data DR. For example, out The force data determination circuit 540-0 has input terminals T to T, and the output data determination circuit 54

 01 015

 0-1 has input terminals Τ to Τ. Each output data decision circuit 540

 11 115

 The power terminal Τ is connected to the ΙΖΟ assignment circuit 530 and its output terminal is connected to the selector 520.

 [0092] With such setting of the read data processing circuit 500C, first, the logic selection signal LSEL is set. Thus, in each of the output data determination circuits 540, desired η input terminals Τ are identified as Ν input terminal forces. Subsequently, the assignment signal ASGN input to the assignment circuit 530 is set. As a result, the η input terminal repulsive forces used in each of the output data determining circuits 540 are respectively associated with η I ΖΟ.

FIG. 18 is a block diagram showing a configuration of one output data determination circuit 540. Here, as an example, the configuration of the output data determination circuit 540-0 is shown. The output data determination circuit 540-0 includes a plurality of majority logic circuits 541a to 541g, a selector 542, and a selector 543. Multiple majority logic circuits 541a, 541b, 541c "'541g are 1 majority logic circuit, 3 majority logic circuit, 5 majority logic circuit ... 15 majority logic circuit. 1 majority logic circuit 541a is a majority operation The logic selection signal LSE L0 is input to the selector 542 and the selector 543. The output data decision circuit 540-0 has a maximum of 15 readouts. Data DR is input Input from IZO allocation circuit 530 to each of input terminals T to Τ.

 01 015

 The read data input is referred to as read data D to D.

 01 015

 For example, assume that the logic selection signal LSEL0 is set to “5” (n = 5). At this time, the output data determination circuit 540-0 selects five input terminals Τ to か ら from the 16 input terminals T to T based on the logic selection signal LSEL0. Therefore, the assigned signal

01 015 01 05

 ASGN to ASGN are the five input terminals T to T power memory cell array 10

01 05 01 05

It is set to be associated with 0 (1 / 0-2, 3, 5, 6, 10). After that, five read data DR are read from the five memory cell arrays 100, as in the above-described embodiment. These five read data DR pass through the ΙΖΟ assignment circuit 530 and are input to the input terminals T to T as read data D to D, respectively. logic In response to the selection signal LSELO, the selector 542 outputs the read data D to D

 01 05 Outputs to voting logic circuit 541c (5 majority logic circuit). The majority logic circuit 541c performs the majority operation to read data D to D output data one output data Do

 01 05

 Determine ut. The selector 543 selects the majority logic circuit 54 lc in response to the logic selection signal LSEL0 and receives the output data Dout from the majority logic circuit 541c.

Similar operations are performed when other majority logic circuits 541a to 541g are selected.

 When the majority logic circuit 541a is selected, the input input from the input terminal T is read.

 01

 Data D passes through the majority logic circuit 541a and is output as output data Dout as it is.

01

 It is powered. Further, the configuration of the write data processing circuit 400 in the present embodiment is the same as the configuration shown in FIG. 14, FIG. 15A, and FIG. 15B.

[0096] According to MRAM 200 according to the present embodiment described above, the following effects can be obtained in addition to the effects of the first and second embodiments. When the majority operation is performed using a lot of read data DR, the data discriminability is improved, but the memory capacity of the chip is reduced. According to the present embodiment, it is possible to flexibly set a majority logic circuit that is composed of only the combinations of IZOs that make up GIZO. Therefore, it is possible to set the contents of the logic selection signal LSEL and the allocation signal A SGN so that the storage capacity is maximized while maintaining excellent reliability. As a result, a chip having optimum performance can be obtained. Further, the chip non-defective rate is further improved, and the manufacturing cost is further reduced.

[0097] (Fourth embodiment)

 In the first to third embodiments, n memory cells 10 constituting the group cell GC are arranged in different n memory cell arrays 100. According to the present embodiment, the n memory cells 10 constituting the group cell GC are arranged in the same memory cell array 100.

FIG. 19 is a block diagram showing a configuration of MRAM 200 ′ according to the embodiment of the present invention. The MRAM 200 ′ includes a memory cell array 100 ′ in which a plurality of memory cells 10 are arranged in an array, a plurality of write word lines 51, a plurality of read word lines 52, and a plurality of bit lines 61. The plurality of bit lines 61 are arranged so as to cross the word lines (51, 52). Each of the plurality of memory cells 10 includes a write word line 51 and a read word. It is provided corresponding to the intersection of the line 52 and the bit line 61. The plurality of memory cells 10 include a reference cell 10r used for reading data. Each memory cell 10 has a TMR element 1 as in the first embodiment (see FIGS. 1A and IB).

 In the present embodiment, n memory cells 10 among the plurality of memory cells 10 constitute a group cell GC. For example, as shown in FIG. 19, three adjacent memory cells 10 surrounded by a dotted line constitute a group cell GC (n = 3). Speaking of this viewpoint, it can be said that the memory cell array 100 'according to the present embodiment is composed of a plurality of group cells GC arranged in a matrix. A reference cell group GRC is composed of three reference cells 10r.

 In each memory cell 10, the TMR element 1 is interposed between one of the plurality of write word lines 51 and one of the plurality of bit lines 61. Here, n memory cells 10 constituting each group cell GC are controlled so that the same data is written. Therefore, the n memory cells 10 (group cells GC) are connected to the same write word line 51 among the plurality of write word lines 51 and to the same bit line 61 among the plurality of bit lines 61. It is preferable to be interposed between them. As a result, the same current acts on the n memory cells 10. Therefore, it becomes easy to simultaneously write the same data into the n memory cells 10.

For example, as shown in FIG. 19, in each group cell GC, three memory cells 10 are arranged along the Y direction. The plurality of bit lines 61 are also arranged along the Y direction. On the other hand, each write word line 51 is arranged to cross a plurality of group cells GC along the X direction. Here, in an area corresponding to one group cell GC (area surrounded by a dotted line), the write word line 51 is bent so as to cross all the n memory cells 10. However, in the region corresponding to each memory cell 10, the write word line 51 is arranged along the X direction. As a result, the n memory cells 10 constituting the group cell GC are arranged corresponding to the intersection of the same write word line 51 and the same bit line 61. Each memory cell 10 is sandwiched between a write word line 51 along the X direction and a bit line 61 along the Y direction, as shown in FIG. At this time, in each memory cell 10, the TMR element 1 is arranged such that the “easy magnetic axis direction” of the spontaneous magnetization in the free layer 2 is along the X direction. Therefore, the Y direction indicates the “difficult magnetization axis direction” of spontaneous magnetization in the free layer 2. Since a certain write word line 51 is bent in an area corresponding to a certain group cell GC, the magnetic field generated by the current flowing through the write word line 51 is different from the magnetic field along the + Y direction and the −Y direction. Includes both magnetic fields along. However, as described above, the Y direction indicates the “difficult magnetic axis direction”, so that the magnetic field along the Y direction only contributes to the rotation direction of the spontaneous magnetic field. In the above-mentioned “parallel state” and “anti-parallel state”, the spontaneous magnetic field に お け る in the free layer 2 and the pinned layer 4 is stabilized along the X direction. Accordingly, even with the arrangement of the write word line 51 shown in FIG. 19, the same data can be written into the n memory cells 10 constituting the group cell GC.

 In addition, as shown in FIG. 19, the MRAM200 ′ further includes an X-side selector 53, an X-side current termination circuit 54, an X-side current source circuit 55, a Y-side selector 63, and a Y-side current termination. A circuit 64, a Y-side current source circuit 65, a read current load circuit 66, a sense amplifier 70, and a read data processing circuit 500 ′ are provided.

 The X-side selector 53 selects a selected write word line from the plurality of write word lines 51 during a write operation, and selects a selected read word line from the plurality of read word lines 52 during a read operation. The X side current termination circuit 54 terminates the write word line 51. The X-side current source circuit 55 is a current source that supplies a predetermined current to the selected write word line during a write operation. The Y-side selector 63 selects a selected bit line from the plurality of bit lines 61. The Y side current termination circuit 64 terminates the bit line 61. The Y-side current source circuit 65 is a current source that supplies a predetermined current to the selected bit line during a write operation. The read current load circuit 66 is a constant current source that supplies a constant current to the bit line 6 lr connected to the selected bit line and the reference cell 10r during a read operation.

[0105] Data is written to the group cell GC as follows. First, write data DW and address data indicating the target group cell GC are supplied to a controller (not shown) that controls reading and writing in the memory cell array 100 ′. With this control signal from the controller, the X-side selector 53 selects the selected write word. The X-side current source circuit 55 supplies a predetermined current to the selected write word line. Further, the Y-side selector 63 selects a selected bit line by a control signal having a controller power, and the Y-side current source circuit 65 supplies a predetermined current to the selected bit line. As a result, the write data DW is written into the group cell GC designated by the address data. However, when there is a “defective memory cell”, a write error occurs.

 [0106] Further, data is read from the group cell GC by sequentially reading data stored in each of the n memory cells 10. Reading data from one memory cell 10 is performed as follows. First, address data indicating a target cell is supplied to the above-described controller (not shown). Based on the control signal from this controller, the X-side selector 53 selects the selected read word line, and the Y-side selector 63 selects the selected bit line. The read current load circuit 66 supplies a constant current to the selected bit line and the bit line 6 lr connected to the reference cell 10r. As a result, the voltage of the selected bit line becomes a “read voltage” corresponding to the resistance value of the TMR element 1 of the selected memory cell 10. In addition, the voltage of the bit line 61r becomes a predetermined “reference voltage” corresponding to the resistance value of the TMR element 1 of the reference cell 10r. The sense amplifier 70 detects the resistance value of the TMR element 1 of the target cell, that is, the data value stored in the target cell by comparing the read voltage with the reference voltage. The “read data DR” read in this way is output to the read data processing circuit 500 ′. The same read operation is repeated by using the same selected bit line for all the n memory cells 10 constituting the group cell GC.

Read data processing circuit 500 is connected to a plurality of bit lines 61 via sense amplifier 70. The read data processing circuit 500 ′ includes n latch circuits 81, 82, 83, and a data output circuit 90. As described above, when the read operation is completed for all the n memory cells 10, n read data DR are stored in the n latch circuits. The data output circuit 90 determines one output data Dout output to the outside based on the n read data DR. In particular, when n is an odd number, the data output circuit 90 determines one output data Dout from n pieces of read data DR by performing a majority operation. For example, if n is 3, then 3 In each of the latch circuits 81, 82, 83, three read data DRO, DR1, DR2 are stored. At this time, the data output circuit 90 is a three-majority logic circuit (see FIG. 8A), and determines one output data Dout using the read data DRO to DR3.

 Next, an example of a read operation according to the present embodiment will be described with reference to FIG. 20 and FIG. Here, the case where n is 3 is shown as an example. At time tO, the signal ZRE input to the read current load circuit 36 changes to low level. As a result, the memory cell array 100 is changed to the read mode. Next, at time tl, the bit line activation signal RBL changes to High level, and a certain bit line 61 is selected as the selected bit line.

 Next, at time t2, the read word line activation signal RWL1 for the first memory cell 10 in a certain group cell GC changes to the high level. As a result, a read current flows through the first memory cell 10. At the same time, a read current flows in the reference cell 10r. Next, at time t3, the sense amplifier activation signal SAEN becomes High level, and the sense amplifier 70 compares the read voltage with the reference voltage. Thereby, the data stored in the first memory cell 10 is detected. The detected data is stored in the latch circuit 83 as read data DR0 at time t4.

 [0110] Next, at time t5, the read word line activation signal RWL2 for the second memory cell 10 in the group cell GC changes to the high level. As a result, a read current flows through the second memory cell 10. At the same time, a read current flows in the reference cell 10r. Next, at time t6, the sense amplifier activation signal SAEN becomes High level, and the sense amplifier 70 compares the read voltage with the reference voltage. As a result, the data stored in the second memory cell 10 is detected. The detected data is stored in the latch circuit 83 as read data DR1 at time t7. The read data DR0 moves to the latch circuit 82.

[0111] Next, at time t8, the read word line activation signal RWL3 for the third memory cell 10 in the group cell GC changes to the high level. As a result, a read current flows through the third memory cell 10. At the same time, a read current flows in the reference cell 10r. Next, at time t9, the sense amplifier activation signal SAEN is High. The read voltage is compared with the reference voltage by the sense amplifier 70. As a result, the data stored in the third memory cell 10 is detected. The detected data is stored in the latch circuit 83 as read data DR2 at time tlO. Read data DR0 and DR1 move to latch circuits 81 and 82, respectively.

The data output circuit 90 determines one output data Dout from the read data DR0 to DR2 by executing a majority operation. In FIG. 20, the solid line shows a case where DR0 to DR3 are all “1”. In this case, the output data Dout changes to “1” at time t4, and the value is held during the reading period. A broken line indicates a case where the second memory cell 10 is a defective memory cell, that is, DR0 and DR2 are “1” and DR1 is “0”. In this case, the output data Dout becomes “1” at time t4, becomes indefinite at time t7, and becomes “1” again at time tlO. At time ti l, the read mode ends and the latch circuits 81 to 83 are reset.

 [0113] As described above, also in the present embodiment, one output data Dout is determined based on the n pieces of read data read out from the group cell GC force. Therefore, the influence of defective memory cells is reduced. Therefore, the discriminability of data stored in the memory cell 10 is improved, and the reliability of the device is improved. In addition, the yield of chips is dramatically improved and the yield is improved. Therefore, the manufacturing cost is reduced.

 In addition, one group cell GC is interposed between the same write word line 51 and the same bit line 61. As a result, the same current acts on the n memory cells 10. Therefore, it becomes easy to simultaneously write the same data into the n memory cells 10.

 Furthermore, writing to a certain group cell GC is performed only in one memory cell array 100, not in a plurality of different memory cell arrays. Moreover, only one write word line 51 and one bit line 61 are used in the writing. Therefore, the current required for writing is reduced as compared with the first to third embodiments. That is, an increase in power consumption is prevented.

Claims

The scope of the claims

 [1] a plurality of memory cells each having a magnetoresistive element;

 A write data processing circuit for supplying write data to be written to the plurality of memory cells to each of the plurality of memory cells;

 A plurality of memory cell powers; a read data processing circuit that processes read data to be read and generates output data to be output to the outside;

 Comprising

 During the write operation, the write data processing circuit supplies the same write data to n (n is an integer of 2 or more) of the plurality of memory cells, and during the read operation, the read data processing circuit The circuit determines one output data based on n read data read from each of the n memory cells. A nonvolatile semiconductor memory device.

[2] The nonvolatile semiconductor memory device according to claim 1,

 N is an odd number;

 The read data processing circuit determines the one output data from the n read data by performing a majority operation.

 Nonvolatile semiconductor memory device.

[3] The nonvolatile semiconductor memory device according to claim 2,

 The n memory cells are arranged in the same memory cell array.

 Nonvolatile semiconductor memory device.

[4] The nonvolatile semiconductor memory device according to claim 3,

 Multiple bit lines,

 A plurality of write word lines arranged to intersect the plurality of bit lines;

 The n memory cells are interposed between the same write word line of the plurality of write word lines and the same bit line of the plurality of bit lines.

 Nonvolatile semiconductor memory device.

[5] The nonvolatile semiconductor memory device according to claim 4, The plurality of bit lines are arranged along a hard magnetization axis direction of the magnetoresistive element, and the n memory cells are arranged along the same direction as the same bit line.

[6] The nonvolatile semiconductor memory device according to claim 2,

 The n memory cells are respectively arranged in n memory cell arrays different from each other among N (N is an integer of n or more) memory cell arrays.

 Nonvolatile semiconductor memory device.

[7] The nonvolatile semiconductor memory device according to claim 6,

 The n memory cells are arranged at the same address in each of the n memory cell arrays.

 Nonvolatile semiconductor memory device.

[8] The nonvolatile semiconductor memory device according to claim 6 or 7,

 The read data processing circuit has an output data determination circuit having n input terminals,

 Each of the n input terminals is connected to the n memory cell arrays, and the output data determination circuit receives the n read data of each of the n memory cell arrays and performs a majority operation. To determine the one output data from the n read data.

 Nonvolatile semiconductor memory device.

[9] The nonvolatile semiconductor memory device according to claim 6 or 7,

 The read data processing circuit includes:

 An allocation circuit connected to the N memory cell arrays;

 An output data determination circuit having n input terminals connected to the allocation circuit,

The allocation circuit receives an allocation signal indicating n memory cell arrays associated with the n input terminals of the N memory cell arrays, and refers to the allocation signal and is associated with the allocation signal. The n number of memory cell array powers The received n number of read data are output to each of the n number of input terminals, The output data determination circuit determines the one output data from the n read data by performing a majority operation.

 Nonvolatile semiconductor memory device.

[10] The nonvolatile semiconductor memory device according to claim 9,

 The output data determining circuit sets two of the n read data to '1' and '0' in response to a control signal input from the outside, and then performs a majority operation. The n read data forces determine the one output data

 Nonvolatile semiconductor memory device.

[11] The nonvolatile semiconductor memory device according to claim 6 or 7,

 The read data processing circuit includes:

 An allocation circuit connected to the N memory cell arrays;

 An output data determination circuit having N input terminals connected to the allocation circuit,

 The output data determination circuit selects the N input terminal forces n input terminals based on a selection signal indicating the value of n,

 The allocation circuit receives an allocation signal indicating n memory cell arrays associated with the n input terminals of the N memory cell arrays, and refers to the allocation signal and is associated with the allocation signal. The n number of memory cell array powers The received n number of read data is output to each of the n number of input terminals,

 The output data determination circuit determines the one output data from the n read data by performing a majority operation.

 Nonvolatile semiconductor memory device.

[12] The nonvolatile semiconductor memory device according to claim 11,

 The selection signal is a nonvolatile semiconductor memory device stored in a register connected to the output data determination circuit.

[13] The nonvolatile semiconductor memory device according to any one of claims 9 to 12,

The allocation signal is a nonvolatile semiconductor memory device stored in a register connected to the allocation circuit.

14. The nonvolatile semiconductor memory device according to claim 9, wherein the write data processing circuit receives the allocation signal and associates the n memories with the allocation signal. The same write data is supplied to each cell array

 Nonvolatile semiconductor memory device.

 [15] Multiple bit lines,

 A plurality of write word lines arranged to intersect the plurality of bit lines; a plurality of memory cells each having a magnetoresistive element;

 A read data processing circuit connected to the plurality of bit lines;

 Comprising

 The plurality of memory cells are arranged at intersections of the plurality of write word lines and the plurality of bit lines, respectively.

 Among the plurality of memory cells, n (n is an integer of 2 or more) memory cells have the same write word line of the plurality of write word lines and the same of the plurality of bit lines. Interposed between bit lines,

 The read data processing circuit determines one output data to be output to the outside based on n read data read from each of the n memory cells via the same bit line.

 Nonvolatile semiconductor memory device.

[16] The nonvolatile semiconductor memory device according to claim 15,

 The plurality of bit lines are arranged along a hard magnetization axis direction of the magnetoresistive element, and the n memory cells are arranged along the same direction as the same bit line.

[17] The nonvolatile semiconductor memory device according to claim 15 or 16,

 N is an odd number;

 The read data processing circuit determines the one output data from the n read data by performing a majority operation.

Nonvolatile semiconductor memory device.

[18] A memory cell array in which a plurality of group cells are arranged in a matrix, a plurality of bit lines,

 A plurality of write word lines arranged to intersect the plurality of bit lines,

 Each of the plurality of group cells includes n (n is an integer of 2 or more) memory cells, each of the n memory cells stores data using a magnetoresistive element, and each of the group cells To the cell!

 The n memory cells are interposed between the same write word line of the plurality of write word lines and the same bit line of the plurality of bit lines.

 Nonvolatile semiconductor memory device.

[19] The nonvolatile semiconductor memory device according to claim 18,

 The plurality of bit lines are arranged along a difficult magnetic axis direction of the magnetoresistive element, and the n memory cells are arranged along the same direction as the same bit line. apparatus.

[20] The nonvolatile semiconductor memory device according to claim 18 or 19,

 And further comprising a read data processing circuit connected to the plurality of bit lines, wherein the read data processing circuit converts n read data read from each of the n memory cells through the same bit line. Based on this, one output data to be output to the outside is determined by performing a majority operation.

 Nonvolatile semiconductor memory device.