JPH0278089A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress a software error caused by an alpha-ray, etc., by outputting the stored data of plural memory cells to be assigned to respective addresses through a majority circuit and rewriting the outputted data according to the output signal of the majority circuit. CONSTITUTION:Three memory cells are assigned to each one bit of the stored data correspondingly to the respective addresses of memory arrays MARY1- MARY3, and the memory cells are arranged at a distance equipment to the width of the memory arrays MARY1-MARY3. The stored data of the three memory cells assigned to the respective addresses are either refreshed in a prescribed cycle or selectively sent to an external part. At this time, for the read signals of these memory cells, majority logic is obtained by a corresponding unit amplifier circuit USA of a sense amplifier SA, and while the amplified read signals are alternatively sent through a column switch CSW, complementary common data lines CD and the inverse of CD, and an I/O, the amplified read signals are rewritten through the corresponding complementary data lines to the respective memory cells.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and relates to a technique that is particularly effective when applied to, for example, a dynamic RAM (random access memory). be.

[Conventional technology]

There is a dynamic RAM whose basic configuration is a memory array in which dynamic memory cells are arranged in a grid. In addition, in the above-mentioned dynamic RAM and the like, there is a trench type cell as one means for suppressing soft errors caused by α rays and the like.

A dynamic RAM using trench cells is described in, for example, Japanese Patent Publication No. 12739/1983.

[Problem to be solved by the invention]

In a semiconductor memory device such as a dynamic RAM, the number of memory cells provided corresponding to each address of a memory array is 11 per pinpoint of stored data, as is well known. For this reason, as dynamic RAMs and the like have become highly integrated and memory elements have become smaller, soft errors caused by alpha rays and the like have come to be seen as a problem. Although the trench type cell described above is an effective means of suppressing such soft errors, on the other hand, it complicates the structure of the memory cell and makes the manufacturing process of dynamic RAM long and complicated. do. As a result, dynamic RA
The yield of M is lowered and its cost reduction is limited.

The purpose of this invention is to reduce the soft error rate without complicating the memory cell structure.
It also provides semiconductor memory devices such as AM.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of memory cells are allocated to one pit of stored data corresponding to each address of a memory array such as a dynamic RAM, and these memory cells are arranged at a predetermined distance from each other.

In addition, the storage data of the plurality of memory cells assigned to each address is outputted via the majority circuit, and
Rewriting is performed at a predetermined cycle according to the output signal of the read majority circuit.

[For production]

According to the above-mentioned means, by using a memory cell with a conventional structure, in other words, without making the manufacturing process longer (or more complicated), soft errors caused by alpha rays in dynamic RAM etc. can be suppressed, and its reliability can be improved. can be increased.

〔Example〕

Figure 1 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Also, the second
The figure shows a circuit diagram of an embodiment of the memory arrays MARYI to MARY3 of the dynamic RAM shown in FIG. 1 and their peripheral circuits. According to these figures, an overview of the configuration and operation of the dynamic RAM of this embodiment as well as its characteristics will be explained. Note that each circuit element in FIG. 2 and the circuit elements constituting each block in FIG. is formed in In addition, in Fig. 2, the MOSFET with an arrow added to the channel (back gate) part is a P-channel type, and the N-channel MOSFET with no arrow added.
It is shown separately from the 3FET.

In FIG. 1, the dynamic RAM basically has three memory arrays MARYI to MARY3 arranged occupying most of the area of a semiconductor substrate, although this is not particularly limited.

Although not particularly limited, the memory arrays MARYI to MARY3 have, as shown in FIG. 2, rrl+1 word lines WO to Wm arranged in the vertical direction and n+1 sets of complementary data 1jtDO/ Do～Dn
-Dn and (m+1)×(n+1) dynamic memory cells arranged in a grid at the intersections of these word lines and complementary data lines.

Each memory cell MC constituting the memo 1j array MARYL to MARY3 includes, although not particularly limited to, an information storage capacitor C3 and an address selection capacitor connected in series, as represented by memory cell MCjk in FIG. M.O.
The drains of the address selection MO5FETQm of m+1 memory cells MC arranged in the same column of each memory array, each including 3FETQm, are connected to the non-inverted signal lines DO to Dn of the corresponding complementary data line or the inverted They are alternately coupled to the signal lines DO to 100τ with a predetermined regularity.

Furthermore, an MO3FET for address selection of m+1 memory cells MC arranged in the same row of each memory array is provided.
The gates of Q m are commonly coupled to corresponding word lines WO to Wm, respectively.

Word lines WO to Wm constituting memory arrays MARYI to MARY3 are connected to corresponding row address decoders RAD.
It is coupled to I-RAD3, and each is alternatively set to a selected state.

Row address decoders RAD1 to RAD3 include, but are not limited to, i
+1-bit complementary internal address signal xQxaxi (Here, for example, the non-inverted internal address signal axQ and the inverted internal address No. 18 axQ are collectively expressed as complementary internal address signal axO.

(same below) are commonly supplied. Furthermore, a timing signal φX is commonly supplied from the timing generation circuit TG.

The row address decoders RAD1 to RAD3 are selectively brought into operation when the timing signal φX is set to a high level. In this operating state, the row address decoders RAD1-RAD3 output the complementary internal address signals axO~! Xi is decoded, and a total of three word lines, one from each of the corresponding memory arrays MARY1 to MARY3, are simultaneously set to a high level selected state.

Although the row address buffer RAB is not particularly limited,
A row address signal supplied via address multiplexer AMX is taken in and held in accordance with timing signal φa' supplied from timing generation circuit TG.

Also, based on these row address signals, the complementary internal address signals qaxo to axi are formed and supplied to row address decoders RADl to RAD3.

Address multiplexer AMX has external terminals AO-A
An X address signal AXO-AXi is supplied via i,
A timing signal φref is supplied from the timing generation circuit TG. Here, the timing signal φraf is selectively set to a high level when the dynamic RAM is placed in refresh mode, although this is not particularly limited.

The address multiplexer AMX is a dynamic type RA
M is in the normal operation mode and the timing signal φre
When f is set to low level, X address signals AXO to AX are supplied in a time-division manner via external terminals AO to At.
i is selected and supplied to the row address buffer RAB as the row address signal. In addition, dynamic type R
AM is in refresh mode and the above timing signal φ
When rer is set to high level, refresh address signals arQ to ari supplied from refresh address counter RFC are selected and supplied to row address buffer RAB as the row address signal.

Although not particularly limited, the refresh address counter RFC performs an increment operation in accordance with the timing signal φrc supplied from the timing generation circuit TG when the dynamic RAM is in the refresh mode, and forms the refresh address signals arO to ari. and supplies it to the address multiplexer AMX.

On the other hand, complementary data lines DO and DO to Dn-Dn constituting memory arrays MARYI-MARY3 are each commonly coupled, although not particularly limited, as exemplarily shown in FIG. 2. These complementary data lines are further coupled on one side to the corresponding unit amplifier circuit USA of the sense amplifier SA, and on the other side to the corresponding switch MO3FETQI4Q1 of the column switch C8W.
It is selectively connected to complementary common data lines CD-CD via Q18 and Q19.

In other words, in the dynamic RAM of this embodiment, three memory cells are allocated per one bit of storage data corresponding to each address of memory arrays MARYI to MARY3, and these memory cells are assigned to memory arrays MARYI to MARY3, respectively. are placed at a distance equivalent to the width of the

As is well known, soft errors caused by alpha rays and the like occur intermittently and locally. For this reason, the arrangement distance of the memory cells, that is, the width of the memory arrays MARY1 to MARY3 is made sufficiently larger than the reach area of energy such as alpha rays, in other words, the area damaged by soft errors. Three memory cells MC arranged at corresponding addresses in each memory array are memory cells MCjk in FIG.
For example, as shown in FIG.
By simultaneously bringing the data lines Dk and the like into the selected state, the data lines Dk and the like are simultaneously coupled to the corresponding common complementary data lines Dk, Dk, and the like.

Sense amplifier SA connects memory arrays MARYI to MAR
fi+1 unit amplifier circuits [including JSA] provided corresponding to each complementary data line of Y3. These unit amplifier circuits USA are, although not particularly limited, as represented by the unit amplifier circuit USAk in FIG.
3FETQ2 and N-channel MOS F E ”r
' Q l 2 and P channel MO3FETQ3
and two Cs consisting of an N-channel MO3FETQ13.
Contains a MOS inverter circuit. The input terminals and output terminals of these CMOS inverter circuits are cross-connected to each other, thereby forming a latch that serves as a storage element of a dynamic RAM.

Although not particularly limited, the unit amplifier circuit USA of the sense amplifier SA is supplied with the power supply voltage of the circuit via a P-channel drive MO3FETQI and a common source line SP, and is supplied with an N-channel drive MO3FETQI and a common source line SN. The ground potential of the circuit is supplied through the circuit. The gate of the drive MO3FETQll is supplied with a timing signal φpa from a timing generation circuit TG, although it is not particularly limited.
is supplied, and the inverted signal of the timing signal φpa by the inverter circuit N1 is supplied to the gate of the drive MO3FET QI.

The driving MO3FETs QI and Qll are both turned on when the timing signal φpa is set to a high level. As a result, the unit amplifier circuit USA of the sense amplifier SA is selectively brought into operation according to the timing signal φpa.

In this operating state, each unit amplifier circuit USA of the sense amplifier SA is connected to the memory cell MC coupled to the selected word line of the memory array MARYI to MARY3 via the corresponding complementary data line DO-DO to Dn-π. The minute readout signal outputted by the microcomputer is amplified and made into a high-level or low-level binary readout signal.

As mentioned above, the dynamic RAM of this embodiment has 3
It has three memory arrays MARYI to MARY3, and three memory cells arranged at corresponding addresses of these memory arrays are connected to complementary data lines DO/π-Dn-Dn.
are simultaneously put into a bonded state. Therefore, the amount of level change ΔV that occurs on each complementary data line when the memory cells are connected is as follows: Δ■=3× when the stored data held in the three selected memory cells is the same ΔV. Further, when one of the stored data held in the three selected memory cells is inverted by, for example, α rays, a part of it is canceled out, so that ΔV=ΔV. Here, ΔV indicates the amount of change in the level of the complementary data line due to the minute read signal output from one selected memory cell.

In other words, in the dynamic RAM of this embodiment,
Each unit amplifier circuit USA of the sense amplifier SA connects three memory cells arranged at corresponding addresses of memory arrays MARYI to MARY3 to a corresponding complementary data line DO-.
Do to Dn- are simultaneously coupled below to form a majority voting circuit for read signals output from these memory cells. Needless to say, each unit amplifier circuit USA of the sense amplifier SA has the ability to expand the amount of change in level of the complementary data line to a binary read signal of high level or low level even when the amount of change in level becomes ΔV. . Unit amplifier circuit U corresponding to sense amplifier SA
The binary readout signal amplified by SA is transferred from the column switch C8W to the complementary common data line C, as will be described later.
It is alternatively sent out via the D-CD and data input/output circuit I10. Also, the corresponding complementary data line DO/Dτ
~Dn-Dτ to rewrite the 21+1 memory cells coupled to the selected word line. This refreshes the data stored in these memory cells.

As exemplarily shown in FIG. 2, the column switch C8W includes n11 pairs of switches MO3 provided corresponding to each complementary data line of the memory arrays MARY1 to MARY3.
Includes FETQI 4, Q15 to Q18, and Q19. One of these switches MO3FET is coupled to the corresponding complementary data lines DO to Dn-D, respectively, and the other is commonly coupled to the complementary common data line CD-CD.

Furthermore, the gates of each pair of switches MO3FET are commonly coupled, and the corresponding data line selection signal Y O-Y n is supplied from the column address decoder CAD.

Column switch C5W switch MO3FETQ14・
Q15 to Q1B and Q19 are selectively turned on when the corresponding data line selection signals YO to Yn are alternatively set to the NO level. As a result, the corresponding complementary data 1ji (DO·DO to Dn-π) of the memory arrays MARYI to MARY3 are selectively connected to the complementary common data lines CD-CD.

Column address decoder CAD is supplied with i+1 bits of complementary internal address signals ayO to ayi from column address buffer CAB, although not particularly limited thereto, and is supplied with timing signal φy from timing generation circuit TG.

The column address decoder CAD is selectively brought into operation when the timing signal φy is set to a high level. In this operating state, the column address decoder CAD receives the complementary internal address signal ayQxayi.
is decoded and the corresponding data line selection signal YO~Y
Alternatively, n is set to a high level.

Column address buffer CAB connects external terminals AO to Ai
The Y address ('JT number AYO-AYi) supplied in a time-sharing manner via the timing generator TG is taken in according to the timing signal φac supplied from the timing generation circuit
Hold. Moreover, these Y address signals AYO=AY
Based on i, the complementary internal address signal ayQ~yi
is formed and supplied to the column address decoder CAD.

The complementary common data line CD-CD is connected to the data input/output circuit I1.
Combined with 0. The data input/output circuit I10 includes, but is not particularly limited to, a data input buffer and a data output buffer. Among these, the input terminal of the data input buffer is coupled to the data input terminal Din, and its output terminal is
It is coupled to the complementary common data line CD-ττ. Although not particularly limited, the data manager 1 is supplied with a timing signal φwe from a timing generation circuit TG. On the other hand, the input terminal of the data output buffer of the data input/output circuit I/'0 is coupled to the complementary common data line CD-CD, and its output terminal is coupled to the data output terminal ()ouL. A timing signal φ08 is commonly supplied to the data output buffer from the timing generation circuit rG.

The data input cover sofa of the data input/output circuit I10, when the dynamic RAM is set to the write mode, has the timing signal φwe set to a high level.
Selectively activated.

In this operating state, the data input buffer uses the write data supplied via the data input terminal Dλrl as a complementary write signal, and uses the complementary common data line CD -
Transfer to CD.

The data output buffer of the data input/output circuit I10 is selectively activated when the timing signal φOe is set to a high level when the dynamic RAM is in the read mode.

In this operating state, the data output buffer outputs data from corresponding complementary data lines DO and D (1
-Dn-D-T and complementary common data 1JlcD-8, further amplifying the binary read signal outputted,
The data is sent to the outside via the data output terminal Dout.

The timing generation circuit TG forms the above-mentioned various timing signals based on the row address strobe signal RAS, column address strobe signal CAS, write enable signal WE, and refresh control signal RF supplied as control signals from the outside. supply to the circuit.

By the way, the dynamic RAM of this embodiment is put into a refresh mode by setting the refresh control signal RF to a low level at a predetermined cycle. At this time, the dynamic RAM increments the refresh address counter RFC according to the timing signal φre, and outputs its output signal, that is, the refresh address signals arQ to a.
The word line specified by ri is alternatively selected. This allows n to be coupled to the selected word line.
The data stored in +1 memory cells is amplified by the majority circuit, ie, the corresponding unit amplifier circuit USA of the sense amplifier SA, and rewritten via the corresponding complementary data line. In this embodiment, the period in which the refresh operation is performed sufficiently covers the information retention time of the dynamic memory cells, and the three memory cells to which the same address is assigned are free from inversion failure of stored data due to alpha rays, etc. A predetermined time is set such that the probability of double occurrence is sufficiently small.

As described above, the dynamic RAM of this embodiment is
The basic configuration is a memory array MARYI to MARY3 in which three memory cells to which the same address is assigned and the same storage data is written are arranged in a grid pattern. The dynamic RAM includes a sense amplifier SA consisting of n+1 unit amplifier circuits USA provided corresponding to the complementary data lines DO/DO to Dn-Dn of the memory array. These unit amplifier circuits USA constitute a majority voting circuit for read signals output from these memory cells by simultaneously bringing three corresponding memory cells of the memory arrays M ARY 1 to MARY 3 into a coupled state. do. Majority logic is taken by the corresponding unit amplification circuit of the sense amplifier SA, and the amplified read signal is selectively output via the column switch C3V/, the phase I common data line CD-CD, and the data input/output circuit I10. The data is sent out and rewritten into each memory cell via the corresponding complementary data line. The dynamic RAM of this embodiment further has a refresh mode for performing the above-described rewriting operation at a predetermined cycle.

In other words, in the dynamic RAM of this embodiment, three memory cells are allocated for each bit of stored data corresponding to each address, and these memory cells are simultaneously affected by one irradiation with alpha rays, etc. They are placed at such a distance from each other. 3 assigned to each address
The data stored in each memory cell is refreshed at a predetermined period that sufficiently covers the information retention time of the dynamic memory cell and prevents soft errors from occurring twice, or is selectively sent to the outside. . At this time, the read signals of these memory cells are sent to the sense amplifier S before being rewritten into the memory cells or sent to the outside.
Majority logic is performed by a majority circuit whose basic configuration is the unit amplifier circuit A. For these reasons, in the dynamic RAM of this embodiment, although it uses dynamic memory cells with a normal structure, the soft error rate occurring in stored data is significantly reduced, and its reliability is improved. be.

As shown in the above embodiment, by applying the present invention to a semiconductor memory device such as a dynamic RAM,
The following effects can be obtained. In other words, (by allocating a plurality of memory cells per one bit of stored data in correspondence with each address of a memory array such as an 11-dyna mini I-type RAM, and outputting read signals from these memory cells via a majority circuit) , the effect of reducing the soft error rate due to α rays, etc. can be obtained.

(2) In the above item +1), a plurality of memory cells assigned to the same address are placed at a predetermined distance so that they do not receive shadow 1 at the same time due to one irradiation with alpha rays, etc. Therefore, it is possible to further reduce the soft error rate caused by α rays and the like.

(3) In the above (paragraph 11), the storage data of multiple memory cells assigned to each address is stored in a predetermined manner that sufficiently covers the information retention time of the memory cells and that soft errors do not occur twice in these memory cells. By refreshing the data at a cycle of

(4) According to (11) to (3) above, by using memory cells with conventional structure, in other words, the soft error rate of dynamic RAM etc. can be reduced without making the manufacturing process long or complicated. This has the effect of increasing reliability.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples, and that various changes can be made without departing from the gist thereof. stomach. For example, in the block diagram of FIG. 1, the number of memory cells assigned to each address, that is, the number of memory arrays, is arbitrary. Furthermore, the dynamic RAM may be one that inputs and outputs multiple bits of storage data through one memory access, or one that includes multiple memory mantles such as memory arrays MARY 1 to MARY 3. It's okay. The dynamic RAM may include a timer circuit for automatically starting the refresh mode, or may start the refresh mode using the CAS before I (AS mode) instead of the refresh control signal RF. Each address decoder may have a multi-stage configuration including a pre-address decoder, or
Address signals AXO to AXi and Y address signal AYO
~AYi may be supplied via separate external terminals. In FIG. 2, multiple memory cells assigned to the same address may be arranged in a common memory array. In addition, the unit amplifier circuit U of the sense amplifier SA
The majority circuit having SA as its basic configuration may include a level determination circuit provided corresponding to each complementary data line. These majority circuits may be provided at positions corresponding to the data output covers of the data input/output circuit I10 by, for example, providing a plurality of sets of complementary common data lines. Movement becomes difficult. The dynamic RAM may employ a shared sense amplifier method or an open data line method. Furthermore, the P-channel MO3FET and N-channel MO3FET constituting the sense amplifier SA may be arranged on both sides of the memory array.The sense amplifier SA is a precharge circuit provided corresponding to each complementary data line. It may also include.

Furthermore, various embodiments are adopted, such as the block configuration of the dynamic RAM shown in FIG. 1, the specific circuit configuration of the memory array and its peripheral circuits, and the combination of control signals and address signals shown in FIG. sell.

In the above explanation, the invention made by the inventors of the present application was mainly applied to the dynamic type RAM, which is the field of application behind the invention, but the invention is not limited thereto (for example, static type RAM, etc.). The present invention is widely applicable to semiconductor memory devices whose basic configuration is at least a memory array in which memory cells are arranged in a lattice pattern, and digital devices incorporating such semiconductor memory devices. can.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. That is, a plurality of memory cells are allocated per one bit of stored data corresponding to each address of a memory array such as a dynamic RAM, and these memory cells are
They are placed at such distances that they will not be affected simultaneously by a single irradiation such as a line. In addition, it outputs the stored data of multiple memory cells assigned to each address via a majority circuit, and also ensures that the information retention time of the memory cells is covered and that soft errors do not occur twice in multiple memory cells. Refresh at a predetermined period. As a result, by using a memory cell with a conventional structure, in other words, the soft error rate of a dynamic RAM or the like can be reduced and its reliability can be improved without making the manufacturing process longer or more complicated.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an example of the memory array of the dynamic RAM of FIG. 1 and its peripheral circuits. MARYI~MARY3...Memory array, S'A・
...Sense amplifier, C3W...Column switch, RA
D1~RAD3...Row address decoder, CAD
...Column address decoder, RAB...Row address buffer, AMX...Address multiplexer,
CAB... Column at, Resbuff 1, Ilo...
Data input/output circuit, RFC...refresh address count, T'G...timing generation circuit. MC...Memory cell, Cs...Capacitor for information storage, Qm...Address selection MO3FET, USA...
-Sense amplifier unit amplification circuit, Q1 to Q3...P channel MO3FET, Q11 to Q19...N channel MO3FET, N1...inverter circuit.

Claims (1)

[Claims] 1. A memory array in which a plurality of memory cells to which the same address is assigned and the same storage data is written are arranged in a grid, and a plurality of memory cells to which the same address of the memory array is assigned. 1. A semiconductor memory device comprising: a majority circuit that receives a read signal from a memory cell. 2. The semiconductor memory device according to claim 1, wherein a plurality of memory cells in the memory array to which the same address is assigned are arranged at a predetermined distance from each other. 3. The semiconductor memory device is provided with a refresh function that reads the stored data of a plurality of memory cells to which each address of the memory array is assigned at a predetermined cycle and rewrites it in accordance with the output signal of the majority circuit. A semiconductor memory device according to claim 1 or 2.